QCNEWS
Photonic quantum company Xanadu and lithography equipment maker ASML announced on September 9 a research collaboration targeting a single nanometer scale roughness figure on the walls of the silicon channels that route single photons, which
A photonic quantum computer processes information with single particles of light running through silicon waveguides, instead of superconducting circuits or trapped ions. Its main unsolved problem is unglamorous: photons leak out of the chip before they finish their job. The leak comes from nanometer-scale imperfections on the waveguide sidewalls, bumps and ridges a fraction of the wavelength of light, introduced when the waveguides are patterned with deep-ultraviolet (DUV) and extreme-ultraviolet (EUV) lithography and the subsequent etch steps.
Xanadu Quantum Technologies and ASML announced on September 9, 2026 a research collaboration to attack that single physical problem. The specific target is line-edge roughness (LER), the sidewall imperfection that, when it roughens the boundary of a waveguide, causes photons to scatter out via Rayleigh scattering. ASML is contributing its advanced exposure systems and computational lithography tooling to find patterning recipes that produce smoother waveguide sidewalls, which Xanadu says will minimize photon loss across complex routing circuits and squeeze-state generation modules (Quantum Computing Report; joint corporate release on GlobeNewswire; The Quantum Insider).
Why this matters runs through error correction. A useful photonic quantum computer is one that runs error-corrected programs; to do that, it needs many physical qubits to encode a single logical qubit, and the number required scales with the loss rate of the underlying hardware. Cutting optical propagation loss therefore directly cuts the physical-qubit overhead, the difference between a lab demonstration and a commercially useful machine. Xanadu has staked its fault-tolerant hardware roadmap on that compression. The collaboration is, in effect, an attempt to move the gatekeeping number on a single manufacturing step.
Both companies have a public read on what the program is and is not. It is a research collaboration, not a process-node purchase, and the release does not name a target loss figure, a process node, or a timeline to a fault-tolerant machine. ASML's participation is also narrower than the wire might suggest: the company is not pivoting into quantum in any broad sense. Its role here is the same one it plays for advanced semiconductor manufacturing, tuning exposure conditions and computational lithography for a specific patterning outcome, applied to a non-leading-edge process step that happens to be the load-bearing one for photonic hardware. The program's industrial weight therefore sits on the sidewall roughness, not on the partnership logo.
The second-order read is on ASML. The company's commercial story is leading-edge EUV exposure tools for advanced logic foundries. A program of this kind is a small, named instance of a different question: whether the same exposure and computational-lithography stack has a role in specialty applications where the load-bearing parameter is not transistor density but waveguide sidewall quality. If the Xanadu collaboration publishes a measured loss improvement, the recipe is in principle portable to other silicon photonics work, including the optical interconnect layer that hyperscale AI datacenters are starting to deploy.
For Xanadu, the move is a small but concrete expansion of its semiconductor-manufacturing footprint as it transitions from research chips toward commercial-scale photonic hardware. For ASML, exposure tools and computational lithography tuned for a specialty application is a familiar assignment; a research collaboration with a public quantum-hardware company is a more public one. Neither side is announcing a finished fault-tolerant photonic machine on any particular date, and the program should be read as a dated, named industrial attempt to move one physical parameter, with downstream compression of error-correction overhead as the payoff if the work succeeds.
The watch item from here is whether the collaboration can publish a measured reduction in propagation loss against a baseline photonic process, and on what timescale. Until that number lands, the most that can be said is that the gatekeeper for room-temperature fault-tolerant photonic quantum hardware is, today, a sidewall roughness figure, and two of the firms with the industrial tooling to move it are now publicly working on the same program.