Why this memory cycle does not look like the last one

The memory chip cycle does not look like the last one because it is no longer driven by the same physics. The old swing was a clockwork rhythm of PC and smartphone demand. This time the swing is governed by a structural new buyer: AI accelerators, which run on high-bandwidth memory, a specialized stack of DRAM tuned to sit next to a GPU. That buyer now competes with conventional server memory for the same fab capacity, and the way it competes is what makes the cycle look different.

TrendForce estimates that in 2027, HBM will consume about 30% of DRAM capacity at the three largest memory makers while producing only 13% of the bits. Each HBM wafer yields far fewer gigabits than a conventional DRAM wafer, because the chips are stacked and tuned for bandwidth, not density. The 30% is a share of the factory, not the market. The remaining 13% of bits has to cover every other use case on 70% of the capacity.

That is why conventional server DRAM overtook HBM in profitability in Q1 2026, even though HBM is the headline story. HBM is locked into longer-term contracts negotiated before the latest spot surge. Spot and contract prices for conventional server DRAM caught up and passed them, because supply was already pinched. The two products are pulling each other up.

The brakes are visible. SK Hynix has approved about $38.3 billion in new fab investment; Samsung and Micron are adding capacity in parallel. TrendForce still projects DRAM bit supply growing roughly 24% in 2027, enough to ease the squeeze if every new wafer went to conventional DRAM. Most of it will not. Watch the HBM-to-conventional mix in each print, the next capex round, and the contract-versus-spot spread. The mechanism is the ratio, not the price.