HWBRIEF
Energy, memory, packaging, and photonics — using light to move data on and between chips — are taking over from shrinking transistors as AI hardware's real bottlenecks.
At June's LID World Summit 2026 in Grenoble, researchers from CEA-Leti and partner labs made a coordinated case: the next gains in AI hardware will come from system-level co-design, not smaller transistors.
CEA-Leti, the French research institute that runs the annual Leti Innovation Days, hosted the June 23–25 gathering. The agenda moved from device shrinks to architecture, data movement, energy, memory, and packaging as the new bottlenecks.
"Data movement, interconnects, power conversion, and cooling are consuming a growing share of the system budget," said CEA-Leti's Jean-René Lèquepeys. Pascal Vivet pointed to 3D stacking and chiplet designs, small modular dies wired together inside one package, as a way to place memory closer to processors. Eléonore Hardy said photonics is moving inward from rack-level links toward co-packaged optics, where optical components sit next to the chip on the same package.
STMicroelectronics' Sylvie Gellida presented the company's 300-mm silicon-photonics platform at the summit. The synthesis: AI hardware will advance through system co-design, manufacturability, and industrial-scale integration, not isolated device breakthroughs.
The integration bet adds cost, supply-chain complexity, and yield risk, and the framing is partly a hedge against slower near-term process-node gains rather than a guaranteed acceleration. Watch over the next 12–18 months: the share of system cost going to data movement and energy, photonics moving toward co-packaged optics, 300-mm silicon-photonics ramps, and any conference-frame reversal back to transistor-led gains.