AINEWS
ASML and TSMC are pushing the small group of vendors that make blank photolithography stencils to roughly double their size, so the next extreme ultraviolet (EUV) tools can print more chips per pass.
For most of the chip industry's history, every shrink in transistor size has meant smaller inputs into the factory. The announcement on September 7, 2026, from ASML and TSMC reverses that pattern, and that reversal is the story. To keep shrinking transistors on the next process node, the lithography ecosystem needs the opposite: photolithography stencils (called photomasks), roughly double the size of today's, so the EUV scanners that print circuit patterns onto silicon wafers can cover more chips per pass.
The joint initiative, timed for the SPIE Bacus photomask conference and covered by The Register, commits the two companies to a 12-inch photomask pilot line by 2031 and full lithography system readiness for advanced node production by 2033. Today's standard masks are 6 inches square. The doubling looks counterintuitive until the cost-per-die math is on the page.
ASML's High NA EUV scanners, the most advanced tools in the EUV lineup, are the most expensive single piece of production equipment in any fab. Throughput, the number of wafers the scanner can expose per hour, is the only variable that makes the cost-per-die math work. A 6-inch mask is too small to cover the full field the High NA optics can project, so each pass can only expose part of a wafer. Larger masks let one scan expose more die area at once, which means each tool-hour is amortized across more working silicon.
That is the request ASML and TSMC are making, and it is not aimed at the litho tool vendor. It is aimed at a small group of companies most readers have never heard of: the mask-blank vendors, a concentrated group of specialist glass suppliers that includes established players like Hoya and AGC. They make the ultra-flat, low-thermal-expansion glass substrates that photomasks are built on, and the release's "broad industry support" language is where the risk lives. The scanner ecosystem and the fab are aligned. The gating step on the 2031 timeline is whether a small number of blank vendors can scale 12-inch substrates with the defectivity and flatness the new scanners will demand.
The release does not name all participating mask-blank suppliers, does not commit them to specific blank volumes, and does not disclose the cost premium 12-inch blanks will carry relative to 6-inch. That cost premium is the variable that decides whether the cost-per-die math actually closes, and it is also the variable the announcement leaves out.
The second-order effect is supplier concentration. Photomask blank manufacturing is already a concentrated market. Asking that small group to roughly double substrate size, at higher flatness tolerances than any current product, on a 2031 clock, puts the next-node roadmap into the hands of a few companies that have not publicly committed to the timeline. If a single blank vendor slips, the slip propagates into every High NA EUV fab downstream, including TSMC's own advanced-node ramp.
What to watch, concretely: by the end of 2027, a name. The release says "other major suppliers have expressed interest" but does not list them. The first 12-inch blank-vendor announcement that names a committed capacity target will be the first real test of whether the 2031 pilot is a coordinated supply-chain program or a two-company declaration. The SPIE Bacus papers in the months that follow will be the second.