HWNEWS
Why every advanced chip strategy ends up in Hsinchu
Europe's first exascale supercomputer — a next generation, trillion calculation per second machine — and U.S.
Europe's first exascale supercomputer — a next generation, trillion calculation per second machine — and U.S.
Europe's first exascale supercomputer will run on a processor fabricated 6,000 miles from Brussels, in Hsinchu, Taiwan, the small industrial city that has become the single most concentrated node in the global chip industry. That geographic mismatch, between European sovereignty rhetoric and Taiwanese manufacturing reality, is the structural outcome of decades of market-driven cluster gravity. It is also the political bet French President Emmanuel Macron made visible when he visited France's largest supercomputer site, CEA's Très Grand Centre de calcul, the JUPITER supercomputer site, where a Rhea1 sample was on display. The chip was made in Taiwan.
The numbers explain why that visibility matters. Taiwan accounts for more than 60% of global foundry revenue and over 90% of leading-edge chip production, according to figures from the U.S. International Trade Administration cited in EE Times' analysis of the industry. Taiwan's semiconductor industry generated more than $165 billion in 2024, roughly 20.7% of national GDP. No other country combines that share of production with that share of economic output.
The cluster gravity behind those numbers is physical, not metaphorical. Hsinchu Science Park, the industrial estate that grew up around Taiwan's Industrial Technology Research Institute in the 1980s, now hosts TSMC, the world's only contract manufacturer of leading-edge logic at scale, plus a dense supply chain of packaging, testing, and failure-analysis vendors. Cheng-Wen Wu, Taiwan's Minister of the National Science and Technology Council, framed the park as a model in an EE Times interview ahead of InnoVEX 2026, describing a "clustering" approach that combines industry, R&D, and academia in one site. The model is the reason a customer can move from wafer to packaged, tested die without leaving the island.
The advanced packaging layer has become the bottleneck for AI and HPC silicon. TSMC's CoWoS (chip-on-wafer-on-substrate), InFO-PoP, and hybrid bonding flows are the connective tissue that lets GPUs, HBM stacks, and CPUs share a package. The dense concentration of failure-analysis vendors in Hsinchu is a key reason why advanced packaging yield engineering stays close to the fab — the distance between foundry and analysis lab is itself a production parameter for the most advanced packages.
That last point is the part of the story that the European policy debate has not fully absorbed. Hyperscalers build their failure-analysis capability next to their foundry, because the failure modes of advanced packaging are time-sensitive. Europe is now asking a Taiwanese fab to play that role for its flagship exascale machine.
JUPITER is the European answer. It will be Europe's first exascale supercomputer, and its CPU module is Rhea1, designed by French fabless company SiPearl and manufactured on TSMC's 6-nanometer process. SiPearl CEO Philippe Notton has described Europe as lacking a leading-edge foundry, framing the Taiwan relationship as a structural choice rather than a sovereignty one. No European foundry yet has the process node that Rhea1 required.
That framing is the political fault line. "Derisking" is the term EU officials use to describe reducing dependence on any single supplier, including Taiwan. SiPearl's own design choice, putting Rhea1 on TSMC 6nm rather than waiting for a European alternative, runs in the opposite direction. Notton has indicated expectations of raising significant capital for the next two generations, Rhea2 and Rhea3.
The capital structure is also pulling toward Taiwan. SiPearl closed a third Series A tranche with participation from Taipei-based Cathay Ventures, a Taipei-based investor. Notton has said he expects a larger Taiwanese investor role in the next round, drawing an explicit "Taiwan, not China" line on the geographic sourcing of that capital. The framing is consistent with Wu's call in his EE Times interview for sustained R&D investment and collaboration with "democratic free countries," a phrase Wu used to mean the U.S., Europe, and Japan.
The political economy of that collaboration is on display this week in Taipei at InnoVEX 2026, the startup exhibition that runs alongside Computex. The event included SiPearl, QuantumDiamonds, French quantum startup Quobly, and others working on advanced packaging, wide-bandgap power, and quantum hardware. The list itself is a tell. The European names are in Taipei because that is where the packaging, testing, and foundry infrastructure is. The Taiwanese government has used the park model for forty years to make sure that statement remains true.
What to watch next is whether Europe's R&D and capital commitments are large enough to bend the cluster. Notton's fundraising targets, the EU Chips Act subsidies, and ongoing French and German national programs are real, but they are operating against a baseline in which Taiwan produces nine out of every ten leading-edge chips and Hsinchu hosts the failure-analysis labs that keep the most advanced packages yield-engineered. The Rhea1 sample on display at CEA-TGCC is what the current structure produces. The next test is whether Europe can fund a process node, not just a chip design, on the same island or on European soil before the next exascale procurement.