HWBRIEF
Automated Test Equipment catches chip defects at the factory, but AI's power and packaging demands expose failure modes only System Level Test can find.
A chip that cleared every check on the factory floor can still overheat, brown out, or corrupt data once it lands inside a real AI server running a sustained workload. The industry's old definition of a "known good die," a chip that has passed every standard factory check, is changing to acknowledge that gap.
Today's AI accelerators pack more compute into less space through high-bandwidth memory (HBM) stacks, 2.5D/3D packaging, and thousands of through-silicon vias (TSVs) connecting the layers. That density is exactly what makes older Automated Test Equipment (ATE) blind to certain failure modes. ATE is fast and precise at the chip or package level, but it does not run real workloads, exercise system-level thermal stress, or check firmware-to-memory behavior under load.
System-Level Test (SLT) is meant to close that gap. Rather than replacing ATE, SLT stresses the assembled board under conditions that mimic a data center: real AI workloads, full power-delivery paths, thermal stress, and end-to-end firmware. It surfaces power-delivery instability, interconnect weaknesses across HBM, and early-life "infant mortality" failures that only appear under load.
A Teradyne-authored industry explainer on Semiconductor Engineering frames the shift as structural: the boundary of what counts as a validated chip is moving from the die to the system. What remains undisclosed is whether hyperscalers are seeing this gap in production fleets, or how often ATE-only parts are still shipping into racks.