HWNEWS
At sub 2nm — the next chip generation, where transistors are measured in a handful of atoms — the smallest features are only a few atoms wide, and the old step by step model of making, testing, and inspecting chips is collapsing into one workflow.
The next generation of advanced chips has smallest features only a handful of atoms wide. Sub-2nm is the node the industry's leading fabs are now racing to put into production, and it is the point at which a single atom can change how a transistor switches, a gentle test probe can crack an oxide layer, and one stray nanoparticle left behind after a chemical-mechanical polish can scrap a multi-die package worth more than a car.
The industry's response is to stop treating chipmaking as four separate steps. For most of the chip era, building a chip was a sequence: make the wafer, inspect it, probe the dies, slice them up, package them, test the package, ship it. At sub-2nm, those steps collapse into a single workflow that has to be designed end-to-end, because the physics no longer tolerates treating them as separate problems.
"We are seeing process specs that need to be tight in the angstrom range, and metrology specs that need to be in the sub-angstrom range," says Juliette Vandermeer, product marketing manager at Bruker Semiconductor, describing how tight the tolerances have become. Bruker, like other metrology vendors, is pushing X-ray diffraction and tomography deeper into the metal stack to catch microfractures that older optical tools could not see. (Semiconductor Engineering)
Now that the features are smaller, the act of measuring them is part of the damage budget. Harrison says the company is moving customers to sacrificial pads and wafer-level bonding before any test probe touches the die, so the extra-thin substrates and hybrid bonds underneath survive the test. "You're trying to test a chip without destroying it," he says, and the way you do that at this scale is to plan the test into the layout from the beginning. (Semiconductor Engineering)
The same logic is forcing test, metrology, and inspection to share data continuously through the line. Rob Kruger, product management director for multi-die strategy and 3D IP at Synopsys, describes data centers moving to redundant server clusters with hierarchical test servers on every die, running tests both before and after the package is assembled and using the UCIe chiplet interconnect and 3D redundancy to repair around failures. "We are moving margin outside the die," he says, "so that you don't have to declare a die good or bad on its own." (Semiconductor Engineering)
Inspection tools now flag millions of wafer defects per lot. Most of them are noise from process variation that older tools would never have picked up. "The sensitivity has exploded," and the engineering problem has become separating real defects from local process chatter. At 2nm and below, the electrical and the physical views have to be merged. Teams have been promoting what they call "Margin Agents", collections of on-chip monitors that ask how much safety margin a particular buried circuit domain actually has once thermal coupling through a 3D stack is included. (Semiconductor Engineering)
Behind the engineering changes is a reorganization of the factory itself. The industry has shifted to virtual capabilities: modeling and optimization that has to cover the full variation space, rather than just one process step. "Hundreds of processes must come together," and you can no longer map the variation space with hardware alone. An orchestration layer connects product lifecycle, ERP, and MES systems with engineering and yield data, so that an AI system can help determine where a wafer that passed test should be routed for packaging. (Semiconductor Engineering)
The reason this reorganization is happening now, rather than at the 7nm or 5nm nodes where the same physics constraints already existed at a smaller scale, is that AI demand has pushed the most valuable chips into chiplet stacks and 3D packages, where one bad die or one stray particle in the bonding interface can scrap the whole package. As the industry moves from 3nm to 2nm and below, the share of advanced packages using that style of integration keeps growing,, and the cost of any one failure climbs with it. The most valuable chip in 2026 is rarely a single piece of silicon; it is a stack of chiplets bonded together with hybrid bonds and through-silicon vias. (Semiconductor Engineering covers the same structural shift in its multi-die coverage here)
The next node is the first one where the long-standing separation between making a chip, measuring it, testing it, and shipping it no longer holds. The tools the leading vendors are shipping now, from sacrificial probe pads and wafer-level bonding to on-chip margin monitors and lifecycle orchestration layers, are designed to run as one workflow rather than a chain of independent stations, and the data-center market is already running periodic in-field tests to drive preventive maintenance.