What It Would Actually Take To Build A p-type Atomically-Thin Transistor In A Real Fab

Industry has spent two decades shipping n-type oxide transistors. IGZO and its relatives already run display backplanes for OLED TVs and are starting to climb into the back-end-of-line logic layers (the upper metal-and-insulator stack built after the transistors themselves are formed on a chip). The p-type partner has lagged, and complementary oxide circuits, plus the dense monolithic 3D chip stacks they unlock, stay a roadmap item until it catches up.

A July 2026 review in Nature Communications Engineering from Stanford and Hanyang consolidates the manufacturing problem into four coupled constraints, in the order a fab line would actually execute them: growth first, contacts second, doping third, and downstream stability last. A BEOL-compatible p-type 2D transistor is not one engineering problem. It is four, and a real fab flow has to solve all of them at the same time, because progress on one without the others does not unlock the circuit. That matters for the industry's next architectural lever: monolithic 3D integration, where logic layers are stacked directly above one another rather than placed side-by-side, and for CFET-style architectures, where nFET and pFET fins are folded into a single footprint to keep density climbing as planar scaling has run out of room. Every realistic 3D roadmap assumes a p-channel oxide transistor that does not yet exist under a real BEOL thermal budget.

The first constraint is growth temperature. A 2D channel, a material just one or a few atoms thick such as WSe2 or MoS2, has to be deposited directly on a metal interconnect stack without melting it. "Transfer-free" growth at BEOL-compatible temperatures (around or below 400°C) is the lever, and the SemiEngineering summary of the review is blunt that the synthesis recipes that work in a research MOCVD chamber do not transfer cleanly to a 300mm production line.

The second is contact resistance. Clean van der Waals contacts, metal-to-channel bonds held by weak atomically clean interfaces rather than chemical bonds, look ideal on paper. In practice the contact metal and the channel intermix under thermal load, and the contact resistance creeps back up. The imec December 2025 disclosure and the Semiconductor-Today write-up point to a record on-current (Imax=690 µA/µm in a WSe2 pFET) but pair it with capped AlOx/HfO2/SiO2 layers from Intel and TSMC-supplied WSe2 monolayers, evidence that the contact problem is being chipped at, not solved.

The third is doping. A p-type 2D channel needs carriers introduced without disordering the lattice, and the imec context shows TSMC exploring phosphorus doping on the n-type side and palladium contacts on the p-type side as two workarounds for two different channel materials. The fourth constraint clusters three failure modes the review treats as one lever: suppressing channel crystallization, volatility, and interdiffusion during downstream BEOL steps. Any one of these turns a working demo into a non-working chip.

Adjacent industry activity, much of it summarized in the SemiEngineering state-of-play piece, shows movement on individual levers rather than a delivery. imec is working on 300mm integration with Intel capping layers. CEA-Leti is pursuing "channel-last" 300mm ALD MoS2/WSe2. Samsung is showing MoS2 n-channel passivation and selective growth at IEDM 2025. Each resolves a slice of the four-constraint problem. None resolves all four together.

The review's stated outlook for BEOL p-type 2D semiconductors is a target, not a delivered process. The next milestone worth watching is a single device demo that holds all four constraints at once, on a 300mm wafer, in a flow that does not require a transfer step or a low-yield contact workaround. As of mid-2026, no public program has claimed that combination. Until one does, every 3D logic roadmap is borrowing a transistor that does not yet exist.