What Has to Be Solved Before AI Clusters Stop Running Out of Wires

Co-packaged optics puts the optical networking that carries data between chips directly into the same package as a switch or accelerator, rather than bolting it on as a separate transceiver. The first deployments went into the links between AI training clusters (a cluster being a tightly coupled group of accelerators acting as one computer) sitting in different racks, where the bandwidth-distance problem had outgrown copper. The harder version, optics inside a single cluster, where thousands of AI accelerators share memory and act as one machine, does not exist at scale. The gap between those two stories is the real work.

A recent panel of three optical-interconnect companies convened by SemiEngineering, including Alchip, Astera Labs, and Ayar Labs, put weight on the same gap. Each company covers a different piece of the stack: Alchip designs the host ASICs, Astera Labs builds the switch retimers, and Ayar Labs supplies the optical chiplets. The shared read across the panel: the chip works, the ecosystem does not yet.

The first deployments were in scale-out, and that side of CPO has settled into a normal product cycle. Adit Narasimha, VP and GM of emerging technologies at Astera Labs, argued scale-out had an inherent optics-demand advantage: customers wanted the bandwidth, the volumes were large, and the cost-performance math made sense. That is why hyperscalers can already buy CPO-enabled switches off the shelf. The harder problem on his list was availability, and not of the optics themselves. It is whether the manufacturing and supply chain are ready to build them at the volumes the next generation of AI clusters will need.

That framing is the same one Ayar Labs has been pushing for two years. The company makes the optical chiplets that go into CPO packages, and its own writing describes the transition from proof-of-concept prototypes to manufacturable systems as in progress, not complete. The supply chain it depends on, from silicon photonics foundries to laser sources to fiber-attach lines, has its own qualification cycles and yield curves, and those have to align before scale-up CPO can ship in volume.

Alchip hosts the optics in the ASICs it designs, and its framing in the cross-posted panel write-up puts the same weight on standards and testing. A CPO package pulls together a silicon photonics die, a laser source, fiber attach, the host ASIC, and a thermal envelope that has to hold in a real rack. Each of those pieces has its own vendor, qualification cycle, and yield curve. The bottleneck is the gap between them, not any one of them.

Scale-up turns the ecosystem gap into a deployment problem. A scale-up fabric is what lets thousands of AI accelerators inside one cluster act as a single computer, exchanging data as freely as cores on one chip. To do that, the optical links have to live inside the package rather than plug into the front of a switch. The panel called that work out by name as the open frontier.

The product question is already settled for scale-out: vendors ship, hyperscalers buy. The open frontier is scale-up, and the people closest to it describe the work as ecosystem work, not chip work. Whether that ecosystem can be built fast enough to match the AI cluster roadmaps already on the table is the question the panel did not pretend to answer.