Verification is the budget the chip-design agent loop is built to eat

Verification is the budget chip design cannot shrink, and the iteration loop that runs against it is the first workflow any autonomous agent has been built to own. Semiengineering's industry frame treats AI writing register-transfer level code as yesterday's story; the live fight is the checking cost that decides whether a tape-out slips a quarter. Thousands of engineers spend billions of compute hours a year not inventing logic, but verifying it, and that checking has largely resisted scaling with Moore's law. Cadence's ChipStack AI Super Agent's Level-5 autonomy, announced at Computex 2026, is a vendor-defined rung, not an industry tier. What it claims to own is the loop an engineer runs in their head: take a task, decide what to try, evaluate the output, and try again. The model runs on NVIDIA Nemotron 3 Ultra under the OpenShell runtime, and the part that matters for enterprises is local: a customer's accumulated design knowledge stays on their hardware rather than feeding an opaque cloud. That custody is what turns the announcement from a partnership into a workflow claim. If the loop holds on production silicon, the bottleneck moves from headcount to agent hours, and the multi-thousand-engineer design team gets reorganized around a different constraint. The RTL authorship is the side dish. Verification is the meal.