HWBRIEF
The proposed NAD architecture — the authors' name for a tightly coupled NAND+DRAM cell level design — skips the I/O buffer and data bus between volatile working memory and nonvolatile storage, with a latency reduction claim that rests on the
A University of Seoul team is proposing a hybrid memory architecture they call NAD that tightly couples DRAM and NAND flash at the cell level, so data can move between the two without crossing the I/O buffer and data bus that sit between volatile working memory and nonvolatile storage.
The mechanism, in an IEEE Access paper (vol. 14, pp. 106983–106994, 2026) by S. Kim, J.-H. Ahn, M. Koo, and Y. Kim, is direct, parallel transfer between the DRAM and NAND layers. The authors say this removes the intermediate components used in conventional DRAM+NAND hierarchies. The Semiconductor Engineering write-up frames the benefit as lower data-transfer latency inside the memory hierarchy.
Scope is narrow: one peer-reviewed paper, no fabricated silicon, no commercial partner, and the latency-reduction claim is the authors' characterization, not an independent benchmark. No competing-architecture numbers appear in the captured source. NAD couples the two memories rather than replacing either, and is architecturally distinct from adjacent work like imec's 3D charge-coupled device with an IGZO channel.
What the paper names is a research target, not a product: whether the buffer-and-bus hop can actually be removed, and at what cost in endurance, density, and process complexity.