Two lab demos point past AI's compute wall to the memory that feeds it

The next AI hardware gains are unlikely to come from faster chips. They will come from the memory that has to feed them. Two university research results published this week illustrate both halves of that shift: a vertical chip-stacking method that claims roughly four times the integration density of today's high-bandwidth memory (HBM, the stacked DRAM used next to AI accelerators), and an analog memory cell that runs the "search" operation large AI models perform constantly far faster than a general-purpose processor.

Neither result is a product. Both are lab demos. But the work is converging on the same bottleneck.

A team at POSTECH, working with Korea's KITECH and Texas A&M, has demonstrated a chip-stacking process that bonds ten chips together while they are still in the transfer-printing stage rather than after the fact. Each chip is about 14 micrometers thick. The team's principal investigator, Seok Kim, said the approach yields roughly four times the integration density of current HBM, the stacked DRAM that sits beside every modern AI accelerator. The method is described in a paper on ScienceDirect, with a research summary on POSTECH's site and a trade write-up at Hardware Busters describing the bonding timing.

Researchers from the University of Hong Kong, Fudan University, and National University of Singapore have built an analog content-addressable memory cell, a memory chip that compares what it stores against what you ask it. The chip returns a match score rather than an exact address. The cell uses a two-dimensional MoS2 transistor with an antimony (Sb) contact and reports 36-picosecond latency, sub-0.1 femtojoule per search, and roughly 108× the throughput of a standard CPU on analog Hamming distance, the similarity metric used inside AI classification. That speedup is scoped to that specific operation, not a general-purpose CPU replacement. The result was highlighted in TechXplore's write-up and the SemiEngineering Research Bits roundup that surfaced both papers this week.

The shared mechanism is the same: pull more memory closer to the compute, and let the memory itself do the lookups. That is the architecture on-device AI (facial recognition, voice assistants, personal LLM features running on a phone or laptop instead of in the cloud) depends on. None of this is shipping. The next milestone to watch is whether either team reports a tape-out or a foundry partner in 2026.