AINEWS
EMIB is Intel's silicon bridge approach to stitching multiple dies into one package.
Advanced chip packaging, the layer that decides how many silicon dies can sit inside a single AI processor, now has two of the world's largest foundries building silicon-bridge offerings for it. TSMC is reportedly developing an "EMIB Like" technology with Taiwan's Kinsus Interconnect Technology, modeled on Intel's Embedded Multi-die Interconnect Bridge, according to a Thursday report from The Information carried by Benzinga.
Nvidia is reportedly evaluating Intel's EMIB for a future processor that would fuse four graphics dies into a single package, an architecture associated with its next-generation Feynman GPU, which targets a release around 2028. For the first time, packaging looks like a buy decision the largest AI chip buyer is willing to make on its own merits rather than a foundry default that comes attached to the chip.
EMIB itself is older than the current AI wave. The technology embeds a small piece of silicon, a "bridge," inside the package substrate to route signals between adjacent dies. It lets a foundry mix process nodes, mix die sizes, and build processors larger than any single reticle allows. Intel has used that capability as a differentiator for its foundry business while TSMC's flagship 2.5D offering, Chip-on-Wafer-on-Substrate (CoWoS), has carried most of the AI accelerator load.
The pressure point for TSMC is CoWoS capacity, which remains choked through 2026. That bottleneck is the demand-side reason a parallel EMIB-class offering makes sense. "EMIB Like" and "Quasi-EMIB" are internal nickname labels inside the report, not confirmed product names, and TSMC declined to comment. If the program ships, it would give AI customers a second supplier for the silicon-bridge approach that today is effectively single-sourced through Intel.
The company announced a separate partnership with China's Lens Technology for glass substrate-based advanced packaging aimed at future AI and data center chips. Glass substrates are a different technical track from silicon bridges, but they target the same buyer question: how do you wire together the largest, most power-hungry accelerator packages on the market?
Nvidia's interest in Intel packaging predates the latest report. DigiTimes first surfaced a possible partial shift to Intel in late January 2026, with I/O dies on Intel 18A or 14A paired to EMIB. Nvidia CEO Jensen Huang has since reaffirmed cooperation with Intel on x86 CPU development, and Apple and Nvidia are both evaluating Intel 14A and 18A nodes alongside the packaging question. Friday's pre-market reaction, Intel up 4.62% and TSMC up 3.69%, reflected the same-day sentiment on a potential packaging redistribution.
The open question is execution. TSMC's reported Kinsus partnership is an unconfirmed development program. Nvidia's EMIB evaluation is not a commitment. Intel still holds the named technology, the foundry customers sniffing around its leading-edge nodes, and a separate glass-substrate track with Lens Technology. The largest AI chip buyer now treats packaging as something to be shopped.
CoWoS capacity remains the clock. Until TSMC widens that bottleneck, every credible EMIB-class alternative is doing more than competing on paper.