The wall isn't transistors. It's the space between them.

For fifty years, the chip industry got faster by shrinking transistors. The thing that has actually stopped shrinking is the gap between them, the contacted gate pitch, and the constraint has migrated from device physics into layout. That is why the next decade of compute density is expected to come from going up rather than out. Qing Cao's Nature paper makes that bet concrete: a University of Illinois Urbana-Champaign team stacked three layers of silicon using ultrathin membranes and a low-temperature process that lets the transistors underneath survive the bonding step intact. Previous stacks degraded the layer below because the heat of deposition killed the dopants. Cao's process keeps them alive, which is the unlock, not the cleverness of the stack itself. Wire coverage will frame this as another attempt to extend Moore's law. The mechanism is more specific: contacted gate pitch is fixed, so density now grows by adding floors, not by drawing finer ones. Hyperscalers planning AI buildouts should read this as a sign that the constraint is no longer theoretical. It is an architectural problem with a stack-shaped answer, and Cao's lab just published the cleanest one yet.