AI Won’t Kill Verification IP, But It Will Redefine It

When Frank Schirrmeister talks about what AI is doing to chip verification, he reaches for a phrase that sounds almost like a punchline: the bottleneck has moved from running simulations to writing the specifications that define what you are verifying. He is executive director for strategic programs at Synopsys, one of the two companies that dominate verification IP — and he is not wrong that something fundamental has shifted.

The popular narrative says AI will automate verification into obsolescence. It will not. What it is doing is redistributing the hard problem. Execution got faster. That makes unclear specifications catastrophically expensive instead of just costly.

The accountability gap nobody is talking about

Here is what the narrative misses: the verification crisis AI is creating is not about speed. It is about who owns the failure when a multi-die AI assembly breaks.

Modern AI chips are not single dies. They are packages containing chiplets from multiple vendors — compute tiles, memory controllers, interface logic — each with its own verification IP, each verified in isolation. The problem is that interface failures fall between VIP footprints in a supply chain that was not designed for shared accountability. Nandan Nayampally, chief commercial officer at Baya Systems, which provides chiplet-ready unified fabric and system IP, put it plainly: each vendor owns the verification of its own chiplet, but when a package fails at an interface, it is not just technical complexity — it is a management burden when multiple vendors are involved, each pointing at the other. The multi-vendor supply chain makes the accountability chain ambiguous in a way individual chiplet VIP contracts were not designed to resolve.

Reporter analysis: no vendor contract examined by type0 explicitly covers cross-vendor interface failures at the package level.

"The VIP encodes decades of protocol nuance, interoperability challenges, and silicon learning," said Nidish Kamath, director of product management, Silicon IP at Rambus. "AI tools will empower verification engineers to explore scenarios and spot verification gaps faster, but these tools will sit on top of trusted verification foundations." The foundation is not the problem. The gap between foundations is.

Synopsys appears to be betting that customers managing chiplet supply chains will pay for a single point of VIP coverage across the full protocol stack. Varun Agrawal, product manager for protocol solutions at Synopsys, has described the company building toward exactly that: a unified verification stack that covers the interface between chiplets as well as the chiplets themselves. Cadence has made a similar organizational move with its VIP portfolio expansion — unveiling 10 new verification IP products in November 2025 covering emerging AI chip interfaces including Ultra Accelerator Link, Ultra Ethernet, LPDDR6, and UCIe 3.0 — but no Cadence executive has gone on record making the same single-accountability argument as Synopsys has. Cadence has not responded to questions about whether its VIP expansion is specifically designed to close the multi-vendor interface gap.

Reporter analysis: reading both companies' announcements as making the same strategic bet on single-point accountability is a reasonable inference — but it is not supported by a named Cadence source.

The verification workload is genuinely extraordinary. Large language model sizes double roughly every four months, pushing interface data rates to double every three years, which means AI chip teams now run verification cycles measured in the quadrillions, according to Synopsys. Narendra Konda, vice president of hardware engineering at NVIDIA, appeared alongside Synopsys at the March announcement — a signal of how seriously the accelerator ecosystem is treating the verification problem at scale.

Security is the blind spot

Here is what is not being discussed in the press releases: most VIP was not built to catch security problems. It was built to catch functional ones.

Jason Oberg, a co-founder of Cycuity (acquired by Arteris in February 2026), has been blunt about the gap. Many VIPs are constructed as System Verilog Assertion monitors that check whether functional integration is correct — but they are not designed to detect confidentiality or integrity violations at integration, he told Semiconductor Engineering. When your chiplet supply chain spans three vendors, the attack surface at the interface between them is not covered by any single VIP contract. The functional verification is someone's problem. The security verification is nobody's.

The bottleneck that AI made worse

Verification has always been the expensive part of chip design. Industry estimates widely cite that verification accounts for roughly 68 percent of overall development cycle time — a figure consistently referenced across the ecosystem but difficult to trace to a single primary source. What the number reflects, however, is borne out in how engineering teams describe their current workloads.

The shift Frank Schirrmeister describes is real and durable: AI is compressing execution time, which means the bottleneck moves to specification quality. You can run a simulation in hours instead of months. What you cannot do is fix a vague requirement. AI makes the fast part faster. It makes the hard part — knowing what you actually want — the only thing that matters.

William Wang, CEO of ChipAgents, a startup working on agentic verification workflows, has argued that the next generation of verification tools will need to close the loop between specification and execution automatically — that the manual translation from requirement to testbench is where AI should intervene. If he is right, the market for VIP is not shrinking. It is graduating to a harder problem.

What to watch

The Design Automation Conference runs July 26 through 29, 2026, in Long Beach, California — and it will be where the EDA vendors show whether their bet on unified VIP accountability is credible or aspirational. The technical roadmaps — UALink, UCIe 3.0, the emerging chiplet ecosystems from AMD, NVIDIA, and Intel — will all be there.

Reporter analysis: whether anyone can actually deliver a single throat to choke at the multi-die integration boundary, or whether the accountability gap persists because the vendors' contracts do, is the question worth watching closely at DAC. The answer will determine who wins the verification stack as AI chips get more complex, not less. That is a better story than AI is coming for your jobs. It is also more accurate.

Sources: Synopsys Converge 2026 press release | Semiconductor Engineering | Cadence VIP announcement | DAC 2026 conference schedule