The Tiny Surface Flaws That Decide Whether Quantum Computers Can Scale

A single-nanometer shift in the ambient oxide layer on a superconducting transmon qubit can swing the device's energy-relaxation time, the standard "T1" coherence metric, by up to 2x. A double-blind study of 22 such devices, led by Fermilab's SQMS Center with Rigetti Computing, NIST, Ames National Laboratory, Northwestern University, and the U.K.'s National Physical Laboratory, has now pinned that spread to specific fabrication geometries. The result narrows what "process control" has to mean for quantum foundries. The variance that decides whether fault-tolerant quantum processors are manufacturable at scale is set at the atomic-scale surface, not at the visible scratches and dust that fab lines have historically screened for.

The Applied Physics Reviews paper and its arXiv preprint describe a protocol designed to remove the most common source of bias in materials studies: prior knowledge. Characterization teams at SQMS's Quantum Garage and partner labs cataloged structural and chemical features across the 22 transmons using seven non-destructive and invasive spectroscopy and microscopy techniques, with no access to T1 data. Only after the cataloging was locked did the T1 measurements get correlated with the materials record. The double-blind structure is what makes the rest of the paper's correlations falsifiable rather than anecdotal.

Three correlations land in the SQMS Center research highlight. Single-nanometer shifts in the ambient surface oxide layer dominate the dielectric loss tangent, the intrinsic rate at which an oscillating electric field bleeds energy into the surrounding material, and directly drive the up-to-2x T1 spread. Sharp 10°–15° etched sidewall angles, compared with broad 30° tapered slopes, reduce electric-field storage in lossy surface oxides; the model predicts a 20%–30% T1 improvement at the steeper angle. Substrate trench depth below 20 nanometers, in the geometry adjacent to the qubit's metal electrodes, drives sharp T1 fluctuations, with effects saturating as trenches go deeper.

The fourth finding is a subtraction. Macroscopic imperfections visible to optical inspection, including scratches, dust, and processing residue, exhibited no statistical correlation with T1 in this sample. The conclusion narrows the manufacturing problem rather than widening it. Foundries that built their process control around catching visible surface defects have been measuring the wrong signal. The actionable signal is sub-20-nanometer trench depth, sidewall taper, and a single-nanometer band of native oxide growth.

The fault-tolerance race turns on exactly this kind of spread. A quantum processor's logical error rate drops exponentially with physical qubit count once physical error rates sit below a threshold, and physical error rates track T1 directly. A 2x T1 swing between nominally identical qubits forces a fixed logical error budget to over-provision for its worst devices, and the engineering question becomes how to tighten the distribution rather than how to push the mean. The result points foundries to three geometric levers: oxide growth conditions, sidewall angle, and trench profile.

Three caveats bound the result. Twenty-two devices from one fabrication flow at Rigetti is a clean dataset, but it is a single-foundry sample, and whether the same sub-nanometer oxide sensitivity holds across other fabrication facilities or academic labs is an open question. The 20%–30% etch-angle improvement is a model prediction, not a demonstrated result from a process change; a follow-up run that deliberately varies the sidewall angle and measures T1 would be the natural next step. "No statistical correlation" in 22 devices is a bounded finding for this sample and this loss regime, not a universal claim.

A companion study referenced in the Fermilab release documents niobium hydride precipitates in the same Rigetti qubit family. That is a separate defect channel, and it sits alongside the oxide and etch work as a second materials-level axis the field will need to track.

Quantum hardware variance was a known problem. It is now a measured one, with three specific geometric levers and a clean negative result on visible defects. The two tests that will decide whether the result holds up: tighten those levers in a new fab run and see T1 move, and reproduce the protocol on devices from other foundries. Both are within reach of the teams that did the first study.