HWNEWS
Operators over provision for uptime, so most of a site's wired capacity sits unused. Chip and rack level controls are starting to reclaim it.
AI's power problem is usually told as a grid story: substations, transformers, and multi-year waits for new connections. The quieter story is inside the building. Operators wire far more power into a data center than the silicon ever draws at once, because the site has to survive the failure of any single feed. The industry calls that reserve "stranded power": capacity that is provisioned for the worst case but goes unused in the average hour.
The buildout of AI compute has made stranded power a budget item rather than a footnote. In Utilidata CTO Marissa Hummon's framing, getting a new megawatt onto a site is "one of the biggest time constraints on data center operators' business." A new substation is a multi-year project; reclaiming headroom already inside the fence is a silicon problem, and chip vendors say they are shipping the controls to do it.
The stranded capacity comes from how data centers handle redundancy. The traditional hyperscale pattern is "2n," where every critical feed has a full duplicate. A site with two utility feeds, each loaded at 50%, can absorb the loss of one because the surviving feed was already running at half its rating. The newer alternative, sometimes called "n+1" or, in Hummon's account of Nvidia's vocabulary, "three-makes-four," runs every feed closer to its limit and treats the spare as a single shared margin. In a 3+1 setup, all four feeds might run at 75% so any one of them can drop. Push them to 90% and a single failure forces the remaining three to carry 120% of their rated load, which means load shedding.
Hummon, whose company Utilidata sells power-management software to utilities and data center operators, runs the math for a 2-gigawatt site. Under 2n, the effective capacity is treated as half, around 1 GW. Operators then target 70-80% utilization on top of that, so only about a third of the wired power ever reaches the compute. The other two-thirds sits in reserve, paid for, cooled, and unused. That is the stranded headroom the AI buildout is now trying to convert.
The lever is per-chip control. At Cadence, VP of product marketing for design IP Arif Khan points to the AMBA low-power interface, an on-chip bus standard the industry's chips already use. Its Q-channel handles clock gating, killing the clock signal to idle blocks so they stop switching and stop drawing dynamic power. Its P-channel coordinates multi-state power control across voltage domains. Together they let a chip put parts of itself to sleep without losing state, which is the basic unit of reclaimed power.
Dynamic voltage and frequency scaling (DVFS) is the older lever: when a workload is light, lower the voltage and clock, and the chip draws less power. The new move is to do that on a per-chip basis instead of a per-rack basis. At proteanTecs, VP of systems Noam Brousard describes a layer of in-circuit monitors that watch each die's actual timing margin in real time. Today, supply voltage is set for the worst-case end-of-life part, which means a day-one chip is over-volted. If the on-die sensors say the silicon has more headroom than the worst case assumed, the controller can lower voltage on that specific chip and only ramp it back up when the sensors detect aging. Brousard calls this reclaiming the guard-band, the safety margin the chip industry traditionally leaves on the table.
At the network-on-chip level, SignatureIP's SVP of sales and business development Ewald Liess describes similar mechanisms: clock gating at individual nodes, per-node power states, and the ability to power down a block of the on-chip fabric when traffic patterns allow. Rambus fellow Steven Woo frames the same trend from the memory side, where low-power DRAM states and per-channel power control do for memory what DVFS does for compute. None of this is a single product; it is a stack of standards and IP blocks that have been arriving in shipping silicon.
The system layer is where the savings become measurable. Utilidata's controller runs two loops. A slow loop forecasts the workload's power draw per rack, per row, and per hall, and tells the scheduler where to place jobs. A fast loop runs on the millisecond timescale through the baseboard management controller and Nvidia's GPU management library, capping power and adjusting DVFS on the fly when a feed sags or a workload shifts. The point is to spend the reserve second-by-second without losing the ability to fail over when a feed actually drops.
Reclaiming reserve capacity inside the fence is now faster than waiting for a new substation. The next bottleneck is silicon-side: how much of the power already wired into a site the chips are allowed to draw. Each per-chip voltage tweak, each gated clock domain, and each millisecond power cap is a small conversion of stranded headroom into usable compute.