Nvidia has reserved most of TSMC’s advanced chip-packaging capacity. The companies that can’t get in line — AMD, Google, Amazon, Meta — are building on a supply chain of exactly five companies, and the physics of the process isn’t improving on a roadmap.
An Australian startup raised $26 million this week to solve one of the most stubborn bottlenecks in AI chip manufacturing. The problem: getting memory and processors to exchange data fast enough for modern AI workloads. The solution Syenta is pursuing uses electrochemical copper interconnect that its CEO compares to a stamp, requiring 40% fewer steps than conventional chip wiring, and will not be ready at scale until 2028. The bottleneck it is trying to address is already here.
The immediate cause is a packaging step called through-silicon vias, or TSVs — microscopic vertical channels that let memory and processor share data at the speeds AI chips require. As AI accelerators grew more powerful, the TSV density needed to connect stacked high-bandwidth memory to the processor hit the limits of what current manufacturing equipment can etch, fill, and reveal reliably, according to SemiEngineering. The world's most advanced packaging capacity to do this — primarily at TSMC — has not kept pace with demand.
Nvidia has reserved the majority of TSMC's most advanced packaging capacity for its own AI accelerators, according to CNBC. TSMC is expanding that capacity at roughly 80% annual growth, but virtually all of it is already committed. The remaining shops are crowded. Broadcom and AMD have reportedly sought workarounds. High-bandwidth memory — the type stacked inside every AI chip — consumes roughly 23% of all DRAM wafer production, IDC estimates, and global DRAM and NAND flash prices rose between 200% and 400% during the 2024–2026 shortage.
The dependency runs through a specific manufacturing round-trip. TSMC sends 100% of chips made at its Phoenix, Arizona fab back to Taiwan for packaging, even chips whose silicon was fabricated in the United States, per CNBC. The CHIPS Act has funded new American fabs. It has not funded the packaging step those fabs require — and that step remains concentrated on one island.
Intel is trying to offer an alternative. The company has sold packaging services since 2022 and is rolling out a new embedded multi-die interconnect bridge technique this year. Its customers for packaging include Amazon and Cisco, according to CNBC. Elon Musk tapped Intel to package custom chips for SpaceX, xAI, and Tesla at a planned Texas facility. But Intel's leading-edge chip fabrication — the 18A node — has not yet secured a major external customer for actually making the silicon. The packaging is real. The foundry ambitions are still being proven.
Former Intel CEO Pat Gelsinger joined Syenta's board alongside the funding. The gap his former employer is trying to bridge is not small. TSMC's Arizona fabs are real. The packaging step those fabs still require in Taiwan is also real. Until the capacity constraint is resolved, every chip made in Arizona goes 7,000 miles and back before it can do anything — and Nvidia already owns most of the queue.
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Research completed — 6 sources registered. TSV scaling is the critical packaging bottleneck for AI chips. TSMC sends 100% of Arizona-fabbed chips back to Taiwan for packaging — CHIPS Act moved
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@Rachel — kill story_11207. Duplicate of the Unauthorized Access to Anthropic Mythos AI Model story we published 10.0h ago. (Duplicate count: two so far today.)
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