Multi die (stacked chip) AI accelerators depend on microscopic interconnects that age after deployment, and the industry's answer is to build monitors and self repair into the next chips.
A lane on a stacked AI accelerator goes dark mid-training run, and the data center's failure logs show no obvious defect. The probable cause is a microbump, one of the microscopic solder joints binding multiple silicon tiles inside what looks like a single chip. It degraded under thermal cycling weeks or months after the part left the factory, and the production test that cleared it never had a way to see that failure mode in the first place.
That is the reliability gap the semiconductor industry is now racing to close, and it has become one of the defining constraints on the next generation of AI hardware. As AI compute demand pulls the industry toward multi-die architectures, where a chip is built from several smaller silicon tiles wired together rather than carved from one slab, the number of microscopic interconnects inside each package has multiplied. The factory tests written for monolithic chips were not designed to verify how those joins behave years into a deployment, and the engineering community is rebuilding the discipline from the package outward. Semiconductor Engineering frames this shift as the central test challenge of the AI era.
Microbumps are smaller than the tips of the probe needles used in conventional final test, so they cannot be probed directly. Engineers have responded by adding sacrificial pads so probes can land nearby, and by building physical-aware bump repair into the test plan for the two-die monitor, test, and repair configurations that the architecture now requires. Probing only catches what is wrong at the gate. Once a multi-die package is in service, it needs built-in monitors that watch the lanes, the through-silicon vias, the RDL routing, and the hybrid-bonded interconnects for the slow aging that no pre-ship test can catch.
"Ensuring initial quality is no longer sufficient. Devices must also maintain their integrity throughout their operational lifespan," Peter Orlando, DFT product director for Siemens EDA's Tessent Silicon Lifecycle Solutions, told Semiconductor Engineering. "In-field testing is therefore essential to quickly detect emerging defects, whether caused by silicon aging, environmental conditions, or unexpected stress, especially in mission-critical applications such as hyperscale data centers and automotive systems where uptime and safety are paramount."
The industries placing the largest bets on multi-die accelerators are also the ones with the least tolerance for a silent interconnect failure: hyperscale data centers running frontier model training, and automotive platforms where a chiplet failure can become a safety event. The wider adoption of 2.5D systems and the push toward full 3D-ICs depend on the field being able to monitor, detect, and repair these failures after the chip has shipped, according to the same analysis. AI accelerators are the specific architectural pressure driving that shift, because their throughput demands have made multi-die packaging the default rather than the exception.
The industry's response is concrete and underway. Synopsys and TSMC have published a multi-die monitoring, embedded test and repair flow that gives chipmakers a reusable template for in-field health checks. Synopsys and Intel have collaborated on the first UCIe-connected chiplet-based test chip, which anchors in-field and embedded test to the Universal Chiplet Interconnect Express standard rather than a proprietary bus. UCIe, AIB, and HBM4 already define spare lanes and pins, the physical redundancy a repair routine needs in order to swap a failing lane for a good one. Silicon lifecycle management is moving from a post-silicon service into an architectural input that feeds design-for-test feedback loops.
"Some chips can repair themselves in the field based on feedback from silicon lifecycle management, DFT, and other in-system test methods," Adam Cron, distinguished architect at Synopsys, said in the same Semiconductor Engineering piece. "Many recent standards for interfaces and buses, including UCIe, AIB (Advanced Interface Bus), and HBM4, provide spare lanes or pins."
Spare lanes on paper are not spare lanes in production. The Synopsys-Intel test chip and the Synopsys-TSMC flow are first implementations of an approach whose economics and coverage are still being negotiated across the supply chain. Resource orchestration, which is how a chip decides which monitor lanes to activate and which repair paths to spend silicon area on, is the named constraint on getting full monitor, test, and repair coverage without exploding die cost. The investor side is reading the same gap. Wing VC has framed chip testing as a bottleneck for the AI hardware buildout, which is consistent with the engineering framing here: the constraint is no longer whether the chip works on day one, but whether the industry can keep it working through the multi-year life of a hyperscale fleet or an automotive platform.
Synopsys and Intel have shown the architecture on a test chip. The next twelve months will show whether the rest of the multi-die ecosystem follows before a real-world microbump failure makes the case for them.