The next chip performance jump won't come from smaller transistors, Huawei says

Huawei is making a specific argument about where the next decade of chip performance will come from, and it is not the argument the industry has been running for fifty years. The company says the gains will come from how chips are stacked, packaged, and orchestrated with software, not from making individual transistors smaller. Huawei is using that argument to position itself against Nvidia's chip-scaling playbook.

The shift underneath the claim is real. TSMC, Intel, and AMD are all pouring engineering and capital into advanced packaging, 3D chip stacks, and tighter coupling between silicon and the software that runs on it. But Huawei's specific formulation, the "Tau (τ) Scaling Law," presented at IEEE ISCAS 2026 by Huawei chief scientist He Tingbo, is contested by independent coverage from The Register, SCMP, and Futurum, which read the language as much closer to a marketing slogan than a physical law.

The core claim is concrete enough to argue with. Huawei says its next smartphone chip, Kirin 2026, draws 41% less power at equivalent performance than the Kirin 9030 Pro baseline, with a 5.6% drop in power density, measured at 25°C and 0.9V on the same process node. Those numbers come from a Huawei paper and have not been independently benchmarked. The mechanism Huawei credits is "LogicFolding," a double-layer folding architecture that compresses signal propagation delay by routing signals across stacked silicon layers instead of fighting distance on a single flat die.

The company has nicknamed its vertically stacked chip package the "18-tier pagoda." The codename is a Huawei-internal label, not industry terminology. It refers to a package in which logic, memory, and interconnect tiers are stacked vertically and coordinated through the company's own chip-software-model stack, an approach that sits inside a broader industry turn toward chiplets (small, modular silicon dies that can be mixed, matched, and packaged together) and advanced packaging that TSMC calls CoWoS (Chip-on-Wafer-on-Substrate) and Intel calls Foveros.

The broader industry turn puts the Huawei claim in context. Every leading-edge fab is hitting the same wall: transistor-level scaling is producing diminishing returns, and the next performance jump has to come from somewhere. For TSMC, AMD, and Intel, the answer is packaging and chiplet architecture. For Huawei, the answer is the same plus what the company calls "system-architecture scaling," or coordinated gains across the chip, the package, and the model software that runs on it.

The Register's coverage of the Tau announcement called it "less like Moore and more like marketing," noting that the underlying engineering is real but the "law" language is a competitive claim, not a physical constant. A separate SCMP analysis asked whether the breakthrough is real or merely hype, and Futurum's industry note treated it as a strategic argument about who gets to define the next decade of chip progress, not a settled result.

Huawei is one of several chip-industry voices making the same turn, and the architecture pivot is a category story, not a one-company event. The company's specific claim, that its 18-tier package is a direct counter to Nvidia's chip-scaling playbook, is positioning, not a benchmark. The Register, SCMP, and Futurum have all flagged the same gap between "we are building this" and "this is a law."

Two open questions will determine whether the "law" label holds. The first is whether Huawei's stacked package ships in volume. The second is whether anyone outside the company can independently measure the 41% power claim. IEEE ISCAS accepted the Tau paper. The industry has not yet accepted the law.