The next bottleneck below silicon is the seam, not the channel

For more than a decade, the limit on transistors thinner than silicon has not been the channel material itself. It has been the seam between that channel and the gate insulator above it. Thin the dielectric, and the gate gains control but the boundary scatters electrons and erases the speed. NYCU's result with TSMC Corporate Research, published in Nature Electronics, names that seam as the engineering target and reports a concrete, measurable handle on it.

The work uses epitaxial interface engineering on a molybdenum disulfide channel to deposit a 0.42-nanometer gate dielectric while keeping charge carriers mobile. The published technique treats the atomic boundary as a designed interface rather than a defect to be tolerated, which is the durable idea behind the headline number. Other groups had been improving channel materials; this one engineered the layer where the channel ends and the insulator begins.

The reusable category is interface engineering as the binding constraint on the beyond-silicon path. Whoever learns to grow atomically thin insulators on atomically thin semiconductors without breaking the boundary will set the pace for sub-nanometer devices, regardless of which 2D material they pick.

Two caveats the Nature Electronics paper itself flags: wafer-scale integration and manufacturing are still open, and a single device result is not a chip roadmap.