AI data centers spent the last decade designing around one rule: put a GPU at the center of every rack and treat the rest of the silicon as a host node. That rule is being rewritten by agentic workloads, the AI systems that plan, call external tools, and chain multiple model steps before answering, because those jobs spend most of their time coordinating rather than running a neural-network forward pass.
A typical agentic request might fetch a document, rewrite a query, decide whether to call a tool, run a second model, and assemble the final answer only at the end. Each step is short, latency-sensitive, and moves data through fast memory rather than matrix math. According to a SemiEngineering analysis of the rack-scale shift, that mix is forcing AI infrastructure to stop treating the CPU as a host node and start treating it as the orchestration tier around the accelerator.
The clearest signal is in the silicon ratios. CPU-to-GPU ratios in AI racks have shifted from roughly 1:4 toward 1:1 over the past two years, the same trade analysis notes, as more of the per-request work has migrated outside the forward pass. The rack is being redesigned to host specialized tiers: prefill on one set of chips, decode on another, tool execution and context management on CPUs, with schedulers and I/O layered above and below. The question is no longer which accelerator is fastest. It is how to keep an ensemble of heterogeneous silicon coherent while a model decides what to do next.
Arm has been the most explicit vendor mapping its products to that frame. In its AGI CPU announcement and a paired rack-scale blog post, the company positions its CPU as the silicon foundation for what it calls "agentic AI clouds," with the product page leaning into the same framing. A third-party architecture explainer walks through how the chip's memory subsystem and I/O are tuned for orchestration rather than raw training throughput.
Arm's framing is a vendor claim, not an industry consensus, and the broader roadmap tells the same story without that branding. AMD's enterprise roadmap, covered in a Tom's Hardware report on the Venice, Verano, Helios and CDNA generations, pairs the next-generation Epyc CPU line with a rack-scale platform designed to host accelerators coherently alongside CPU, memory, and network tiers. AMD's Helios chassis, the rack-scale backbone for those pairings, points to the same destination from a different starting architecture. Both vendors are converging on the same composition: a heterogeneous rack rather than a GPU with a host node.
The skeptic case deserves a hearing. Analyst commentary from Chipstrat argues that agentic CPUs are not yet a commodity, because the deciding variables (memory bandwidth, coherent accelerator links like PCIe and CCIX, on-package integration, and the topology of the rack itself) still differ sharply between vendors. ARM-based designs and x86 CPUs may both be sold as "the orchestration tier," but the silicon underneath is still specialized in ways that shape system cost and floorplan.
The gigawatt-scale clusters now being assembled by hyperscalers are an obvious test case. Each rack is being asked to do a specific job in a chain, and that chain is getting longer and more stateful with every agentic workflow that lands in production. Power, cooling, and floor space were already binding constraints at single-gigawatt scale. Adding a CPU tier that cannot be skipped adds a second binding constraint: coherence, the requirement that orchestration silicon can move data in and out of accelerators without becoming the bottleneck it was supposed to replace.
The next architectural decisions are landing in rack reference designs and CPU-vendor SKUs that target coherent acceleration, well ahead of the GPU launches that tend to draw the headlines. The next gigawatt-cluster announcement will be a floorplan story before it is a GPU-count story.