At ECTC 2026, the chip industry's main advanced packaging conference, Intel, TSMC, Marvell, Microsoft, and Lightmatter showed how the physical assembly beneath the silicon has become the next scaling wall, and what each is building to break through it.
The AI industry's scaling story is moving downward. For decades, making a chip faster meant packing more transistors onto a single slab of silicon. The 2026 edition of the IEEE Electronic Components and Technology Conference, known as ECTC and held each spring as the chip industry's main venue for advanced-packaging research, makes clear that question has changed. The bottleneck has dropped beneath the die, into the package: the substrate, interposer, and bridge network that hold multiple dies together and connect them to memory and to each other. Roundups from SemiAnalysis and trade press covering the conference frame 2026 as the year the package, not the transistor, becomes the load-bearing constraint on AI accelerator scaling.
Three forces drive the shift. First, the die itself is now hitting reticle limits: lithography tools can print only so much silicon in one exposure, the maximum is called a reticle, and the largest AI accelerators already approach or exceed it. Pushing past that means stitching multiple dies into one package. Second, HBM4E, the next generation of high-bandwidth memory stacks that ride alongside accelerators, brings packaging pain: per-pin speeds rise and input/output counts roughly double, tightening routing and thermal budgets inside the package. The HBM4E I/O jump and speed uplift are flagged in the SemiAnalysis ECTC roundup. Third, top accelerator parts now draw multi-kilowatt power, which cold-plate heatsinks cannot remove efficiently. Together, these forces make the package, historically a commodity step, into the new engineering frontier.
The clearest packaging bet from ECTC 2026 comes from Intel, which disclosed an EMIB-T integration overview and a forward roadmap. EMIB, short for Embedded Multi-die Interconnect Bridge, is Intel's approach to linking adjacent dies with a small silicon bridge embedded in the package substrate, instead of placing them on one giant circular interposer. The T variant adds through-silicon vias, vertical electrical connections passing through the die, enabling taller stacks and tighter routing. The structural appeal is straightforward: bridges sidestep the wafer-yield penalty of massive circular interposers, where a single defect can scrap an entire package. Per the SemiAnalysis ECTC roundup, EMIB-T is positioned as Intel's path to multi-reticle AI packages without paying the interposer cost of TSMC's dominant CoWoS, or chip-on-wafer-on-substrate, platform.
Marvell attacked the memory side of the package problem. Its custom-HBM proposal moves the HBM interface and PHY logic off the accelerator die and onto a dedicated companion chip, shortening the package-level routes between logic and memory stacks. The motivation is HBM4E again. Doubling I/O and raising per-pin speed makes it hard to land hundreds of HBM signals onto a single compute die without starving that die of area and power. Pulling the PHY out lets the accelerator focus on math and lets the memory interface be optimized on its own die. Framing from TSPA Semiconductor treats this as one of three HBM battlegrounds exposed at the conference, alongside capacity scaling and the thermal and signal-integrity constraints of HBM4 packaging.
Cooling was the third leg of the menu. TSMC and Microsoft demonstrated direct-to-silicon, also called microfluidic, liquid cooling integrated onto the CoWoS platform. Conventional cold plates sit on top of the package lid and pull heat through several layers of material before it reaches the coolant. Microfluidic cooling etches channels directly into the silicon, so coolant flows within microns of the transistors. As SemiWiki's coverage of the TSMC demo frames it, the breakthrough is not exotic new fluids but removing the thermal resistance of the package lid and the thermal-interface-material stack on top of it. The peer-reviewed basis appears in an IEEE ECTC paper documenting direct-to-chip microfluidic integration on CoWoS.
The fourth bet moved interconnects off copper. Both Marvell and Lightmatter brought optical, or photonic, signaling onto the package. Photonic links carry data as pulses of light through silicon waveguides rather than as electrical pulses through wires, sidestepping the resistance and crosstalk that cap long on-package routes at high speed. Lightmatter used ECTC to position its Passage M1000 as a photonic superchip for AI interconnect, with the company's ECTC presence framing the conference as a platform for the manufacturing push behind on-chip photonics. Trade coverage in Semiconductor Engineering makes the underlying point: photonic interconnects only matter once they can be made on the same fab lines as the logic they connect to, which is the manufacturing problem now being cracked.
Read together, these are not five competing announcements. They are five answers to a single constraint. The die has run out of room. The memory interface has run out of pins. The heatsink has run out of thermal headroom. The copper wire has run out of bandwidth. The package, historically the cheapest and most standardized step in chipmaking, is where the engineering capital is going next.
What to watch is which bets cross from paper to product. EMIB-T and custom HBM are tied to next-generation accelerators already in development. Microfluidic cooling and on-package photonics remain at the demonstration or early-shipping stage, and production timing, yield curves, and adoption rates are not yet public for most of them. The honest summary is that the chip industry's center of gravity is shifting from the silicon to the substrate, and the next eighteen months will show how cleanly each of these bets converts.