HWBRIEF
ETH Zürich, Germany's CISPA Helmholtz Center for Information Security, and NYU researchers propose Terracotta, a programmable DRAM memory controller and composable primitives that let new memory techniques ship by configuration, not a chip redesign.
The working memory inside every computer sits behind a rigid contract. The DRAM interface and its memory controller have to be redesigned every time a new memory technique comes along, and that cycle has slowed the path from research idea to deployed chip, according to coverage in Semiconductor Engineering.
A new framework, Terracotta, from researchers at ETH Zürich, CISPA, and NYU, splits that contract into two flexible pieces. Vendors get custom command extensions that fit inside one standardized interface, so a new command does not require a new specification. System designers get a programmable memory controller that they can configure after the chip is already on a board.
The deeper move is compositional. The paper's authors argue that, across in-DRAM computation, lower-latency access, parallelism tricks, maintenance, and reliability fixes, the command and controller structures of many DRAM techniques are similar enough to be built from a shared set of primitives. New techniques become combinations of primitives rather than fresh designs.
The implications land at the pace of innovation. With a programmable controller, in-DRAM compute, latency cuts, and reliability work could move from a research paper to a real system through configuration rather than a silicon respin. The open-source artifact is listed as a MICRO 2026 release; the senior author is Onur Mutlu at ETH Zürich.
Speedups, area, and energy overhead are not in the trade press; those numbers live in the full paper. The contribution here is the design pattern, not a shipping product.