The hardest 10%: where senior engineers still beat AI in chip design

At CadenceLIVE 2026 this month, the company's SVP for digital and signoff, Teng Jinqing, put a number on a question the chip industry has been circling: how much of a chip's design cycle can AI actually take over? His arithmetic: about half.

The math is a stack. Roughly 30% off tool runtime, plus roughly 30% off per-engineer throughput, and a chip design that used to take an elapsed year lands in about six months. Teng, who runs Cadence's digital and signoff group, laid it out that way at the conference; the Chinese-language interview with Leiphone (雷锋网) walks through the assumptions in detail, and a Futurum Group analyst note from the same week puts the wider customer range at 3–10x productivity.

Electronic design automation (EDA) is the software stack that turns a chip specification into the manufacturing files a fab consumes. Cadence, Synopsys, and Siemens EDA are the three vendors whose tools run that pipeline. When Cadence's VP and China GM, Wang Xiaoyu, walks customers through what the math means in practice, the most concrete number is a single block: a large subsystem that took about five weeks of design and verification collapsed to roughly one day using Cadence's ChipStack agent, according to the same Leiphone interview. A separate 4nm high-performance CPU core convergence case closed near senior-engineer quality, with the agent taking over the manual log, constraint, and runloop work that usually eats calendar time.

That is the 90%. Teng argues that AI can now automate 70–90% of the structurally simple, non-extreme-performance regions of a chip: standard cells, connectivity glue, verification scaffolding. The remaining 10% is where the chip has to win. CPU and GPU cores, NPUs, congestion-bound blocks where the layout has nowhere to go, and signoff at 3nm, 2nm, and 1.4nm where a single bad signoff can fail the part. On those blocks, Teng does not see AI alone shipping a usable chip within five years.

Three concrete barriers sit on that horizon. Multi-agent coordination: when the front-end, verification, backend, and signoff agents each optimize for their own metric, they have to be reconciled by something that is not yet a model. Deterministic verification at the most advanced nodes: a hallucinated constraint in a 1.4nm signoff is not a wrong answer to a question, it is a dead chip. And the gap between running a design flow to completion and producing a chip that is competitive in the market. The OpenAI "Jalapeño" project, which the Leiphone piece cites as adjacent context, ran from initial design to tapeout in about nine months, with AI used to explore implementations and shorten design-measure-verify loops, but the work was co-developed with Broadcom, not produced end-to-end by a model. RCR Wireless News covers the same CadenceLIVE announcements in English.

Wang's caveat, from the same interview, is the one customers actually feel. A 2x tool-side lift can be visibly discounted inside the customer, because team structure, division of labor, and collaboration patterns decide how much of the new throughput lands in shipped silicon. Cadence's own CEO, Anirudh Devgan, is pushing AI research top-down across product lines, with ViraStack for analog and InnoStack for digital implementation extending the end-to-end flow from spec to signoff, per the Futurum note.

For working chip engineers, the math is also a career-direction signal. The 90% that AI is good at is the work that used to occupy junior and mid-level engineers on routine blocks: writing scaffolding, hand-running verification loops, sweeping corners. The scarce skill is now the hardest 10%: congestion analysis, signoff judgment at advanced nodes, architectural tradeoffs. That is the same kind of skill-shift that happened when synthesis and place-and-route moved from manual to automated in the 1990s. The difference this time is that the binding constraint sits in the part of the chip where the vendor stack cannot reach, and the customer has to rewire itself to capture the gain.

Teng's five-year horizon is the line to watch. If a competitive advanced-node chip reaches tapeout with an AI agent owning the architectural calls, the rest of the stack will follow on a much shorter clock. If it does not, the 30+30 arithmetic is the ceiling, and the next phase of the chip designer's job is exactly the one Cadence just named.