The Hard Part of AI Isn't the Algorithm. It's the Chip.

AI accelerators are the first chip workload to hit every design-tool silo at the same time. Logic, memory, interconnect, power, thermal, package, software. Each discipline has its own tools, signoff checks, and specialists. AI silicon stresses all of them in parallel, and the result is a new question on the table at this year's Design Automation Conference.

DAC, the chip industry's annual design-automation gathering, has reorganized its Engineering Track around that question. The EE Times preview by program chair Frank Schirrmeister lists roughly 15 sessions and 90 presentations built around one frame: today's tools were not designed for the AI accelerator workload, and the question is whether they can be made to hold.

A 12-high HBM stack shows a 442% increase in maximum IR drop compared with single-die analysis. The traditional power-supply-network assumption, that current flows in a predictable way through the package, breaks when fast di/dt switching hits a flip-chip BGA. The industry's response is hierarchical EMIR analysis, which a reticle-scale data-center SoC reportedly runs 10× faster than the flat approach. At 56G, 112G, and 224G SerDes speeds, distributed dynamic power-integrity flows become the gate the design has to clear.

Broadcom and Synopsys published early thermal analysis for face-to-face 3DIC stacking, the technique of bonding two die together copper-to-copper, correlated to post-silicon measurement within 3°C. Backside power delivery, the layout trick that puts the power rail under the transistors instead of alongside them, reportedly cuts core power by 19.8% and reduces temperature by 9.3°C in next-generation AI processors. AI-driven placement now explores hundreds of thermally constrained scenarios across heterogeneous chiplet stacks, because hand-tuning does not scale to the search space.

Intel's unified library QA framework, per the DAC 2026 program, runs Siemens Solido Crosscheck against 1,000+ cells across 30+ process-voltage-temperature corners, the combinations that decide whether a design holds up across foundries and operating conditions. Standard-cell libraries offer roughly 30 variants per gate type; the theoretical design space runs to millions. AI-driven transistor-level sizing reports double-digit power and timing improvements on industrial silicon. AI parsing of hard-IP integration documents has reportedly saved integration teams up to two weeks and missed zero requirements. Formal verification caught a buried credit-management bug in PCIe Gen6/7 logic in a recent project, a class of error that simulation almost never finds.

Silicon lifecycle management can compress embedded trace by up to 700×, then feed it into an AI inference engine hunting silent data corruption, the kind of failure mode that ships to customers and only surfaces years later. A custom edge neural-processing unit reportedly delivers 100 GMAC/s (billion multiply-accumulate operations per second) in 200K gates, a density figure that depends on tuning both ISA and memory hierarchy to the workload. Ricursive, the startup behind AlphaChip-style recursive design, has a session in the program on closing the loop between AI models and the hardware that trains them.

The argument the program keeps returning to is one borrowed from Simon Davidmann: the AI problem worth solving is not faster flows but expanding what hardware-software systems the industry can verify at all. If the tools hold, the AI accelerator becomes another workload on the same conveyor belt. If they don't, the next round of DAC sessions will show how.

The next test is convergence. EDA silos have always integrated eventually through co-design and signoff convergence. Whether the AI accelerator workload triggers another round of that cycle, or forces a real rebuild of the design toolchain, is the question the 2026 program was built to surface.