3D IC, or three dimensional integrated circuits built by stacking and tightly interconnecting multiple silicon chiplets in a single package, is moving from research to production. The hard part is no longer how to build the stack, but how to design it as one system.
The chip industry is quietly redefining its unit of design. For decades, the die was the thing a team optimized: a single slab of silicon on which a system-on-chip pushed performance, power, and cost to their limits. With the rise of 3D-IC, three-dimensional integrated circuits built by stacking and tightly interconnecting multiple silicon chiplets in a single package, that assumption no longer holds. The boundary that matters has moved. The package is now the chip.
Why now? The short answer is artificial intelligence. AI training and inference workloads have turned memory bandwidth, data movement, and energy per operation into the binding constraints on hardware. The most attractive way to attack those constraints is heterogeneous integration: split a system into chiplets built on different process nodes, then assemble them in a stack or on a high-density interposer so they can communicate at speeds and densities that a printed circuit board cannot deliver. This is how the latest accelerators pair GPU silicon with stacks of high-bandwidth memory, and it is becoming the default template for advanced computing.
The hard part is no longer physics. The hard part is design. Traditional electronic design automation (EDA) flows were built for monolithic SoCs: one die, one floorplan, one set of sign-off checks. A 2.5D or 3D-IC assembly spans at least four physical layers, each with its own optimization trade-offs: the silicon die, the interposer that connects chiplets, the package substrate, and the through-silicon vias or hybrid bonds that tie the stack together. Power delivery, thermal dissipation, mechanical stress, signal integrity, and cost all behave differently in each layer, and they interact in ways a single-die tool was never asked to model.
To close that gap, the industry has converged on a methodology it calls system-level technology co-optimization, or STCO. Where older design technology co-optimization (DTCO) treated the transistor and the cell library as the optimization target, STCO pushes the target up to the full package. Imec, the Belgian research center that has done more than any single institution to articulate the concept, describes STCO as a way of working in which logic, memory, and 3D programs can no longer be researched in separate silos and must instead be done concurrently, driven by system application targets. Imec structures that work around three scaling walls: the memory/bandwidth wall, the power/thermal wall, and the dimensional scaling wall (imec). A 2024 review in Nature Reviews Electrical Engineering treats STCO as a method for running the same kind of optimization jointly across transistors, interconnects, packaging, and the system architecture that ties them together (Nature Reviews Electrical Engineering).
The optimization metric has expanded with it. Where conventional EDA workflows optimize for power, performance, and area (PPA), the literature on chiplet and 3D-IC design now standardizes on a five-axis variant: power, performance, area, cost, and reliability, or PPACR (SemiEngineering). Cost enters because a multi-die assembly is a multi-foundry, multi-process, multi-packaging business, and a design choice that is free at the transistor level can be ruinously expensive once you add the second and third silicon. Reliability enters because every new interface introduces another surface where mechanical stress, thermal cycling, and electromigration can fail: chiplet to chiplet, die to interposer, stack to substrate.
This is the framework that Siemens EDA's Innovator3D IC family sits inside, but it is important not to confuse the framework with any one vendor's tools. The same methodology is articulated in academic literature, in imec's roadmaps, and in the workflows chip companies are quietly building for themselves. Siemens' contribution, as described in SemiEngineering's analysis, is a concrete EDA implementation; it is not the methodology itself (SemiEngineering). For a buyer or investor, the useful question is not who sells 3D-IC EDA, but whose design flow actually spans the whole stack.
That question is about to get harder. Imec's first thermal STCO study of 3D HBM-on-GPU architectures, presented at the IEEE International Electron Devices Meeting (IEDM) in December 2025, is a sign of where the methodology is heading: into workload-specific, application-driven co-design that treats the AI model as part of the optimization problem (imec). The unit of design is still migrating. The interesting question is no longer what is in the package, but who can co-optimize the whole thing at once.