The Chip Industry Is Finally Stopping Designing Hardware and Software Separately

A phone running a large language model on-device, an inference job that has to fit inside a 5-watt thermal envelope, and a software team that ships updates every few weeks. Each of those would once have lived on its own side of a wall inside a chip company. The wall is coming down, and the reason is not that engineers suddenly prefer collaboration. It is that the workload has made the handoff uneconomic.

"Long gone are the days of a hardware team building something then throwing it over the wall to an embedded software team," said Steve Roddy, chief marketing officer at Quadric. "That era died more than two decades ago." (Semiconductor Engineering)

Hardware/software co-design, the practice of one team designing a chip and the software that runs on it together instead of finishing the silicon and handing it off, is not new. It was tried in the 1990s and largely failed. What is new is that the conditions that killed the first attempt have inverted. Software iteration now moves faster than hardware iteration, AI inference workloads have moved onto phones, cars, and edge boxes, and the power and thermal ceiling of those devices no longer absorbs a poorly tuned handoff. The industry's second co-design attempt in roughly thirty years is being forced by physics, not by fashion.

Virtual twin modeling is the layer that was missing in the 1990s. A virtual twin is a simulation of a chip's physical behavior (timing, power draw, thermal response, sensor interfaces) coupled tightly to the software workload that will run on it. The Semiconductor Engineering synthesis calls it the successor to 1990s virtual prototyping, and the difference matters: where the old tools relied on high-level specs and ad hoc prototypes, today's virtual twins let a hardware engineer watch what an AI inference kernel will do to the chip before the design is frozen for manufacturing. The result is a feedback loop that did not exist when the first co-design wave collapsed.

MIPS and GlobalFoundries have bundled their IP and physical AI platform so the chip and the firmware ship from the same roadmap. Normal Computing is building physics-based ASICs whose architecture is co-derived from the inference algorithms they are tuned to run. Quadric is positioning its automotive NPU stack around the same logic, treating the silicon, the compiler, and the model graph as one company's problem. Each is a different flavor of the same answer to the same pressure.

Chip power, cooling, memory bandwidth, and system-level energy budgets are collapsing into a single thermal envelope that has to be optimized end to end. You cannot hand off a piece of that envelope to a separate team and expect the device to meet its battery and performance budget at the same time. Vertical integration across the stack, from silicon to firmware to software to system design, is becoming the engineering response to a thermal and energy constraint that does not split cleanly along the old org chart.

Virtual prototypes are still "not viewed as being an adequate solution for realistic workloads," per the Semiconductor Engineering synthesis. That line is the most credible one in the article for a smart reader, because co-design failed in the 1990s not for lack of interest but because the tools were not good enough to bridge the abstraction gap between hardware description languages and real software. The industry is betting that this time the modeling tools have caught up. A preprint on physics-based ASICs circulating this year makes the same bet in print, though it has not yet been peer-reviewed.

The next test is whether the second attempt survives its first wave of consumer hardware. Phones, edge boxes, and inference accelerators shipping in 2026 and 2027 will tell the story one way or the other: if they meet their battery and performance budgets by treating silicon and software as one design problem, the co-design revival will look inevitable in hindsight. If they miss, the industry will discover, again, that the wall was there for a reason.