The Asymmetric Stall Economy

On modern GPU pipelines, the contract between vendor and compiler has thinned to almost nothing — and what is lost is no longer speed, but a guarantee of correctness. Call it the asymmetric stall economy: a regime where the spec the compiler gets is the chip itself, not the documentation. Aditya Kumar's microbenchmarks on the B200 are the cleanest case. Nvidia publishes no instruction latencies, no pipeline depth, no scoreboard encoding, so the only way to learn the schedule is to run it on real silicon. Once you do, the asymmetry resolves into a single rule: over-stalling is a performance bug, but under-stalling is a silent correctness bug. The mechanism generalizes past one accelerator: when vendor documentation stops covering runtime behavior, static analysis is necessary but insufficient, the test suite does not catch under-stalls, and the hardware raises no exception. The wrong schedule ships as a quiet answer. In that regime, compiler teams don't optimize against a spec — they optimize against the silicon itself, and the speed-correctness trade becomes the only interface the vendor still publishes.