Simulation Speed Is the New Bottleneck in Chiplet Design

In a chiplet design cycle, the question is no longer whether the toolchain can model a 2.5D or 3D stack. It is how many days the team can afford to wait for the answer. That wait, multiplied across the programs that now depend on stacked dies (AI infrastructure, data centers, automotive, and aerospace and defense), is what industry analysis is starting to call the new bottleneck.

The shift is from toolchain capability to iteration speed. The pieces are in place to model electrical, thermal, mechanical, and optical behavior in the same run. What is missing, according to a Semiconductor Engineering analysis, is a loop that can keep up with the design cycle.

The concrete anchor is recent work on multi-fidelity thermal modeling. A preprint from the MFIT group on arXiv reports that finite-element method (FEM) simulations of 2.5D and 3D chiplet systems can run for days, with cost driven by geometric detail, mesh density, and how the stack is parameterized. For a design team iterating on bump pitch, interposer choice, or the placement of co-packaged optics, a multi-day run per pass is the wrong clock.

Multi-physics is not optional in these stacks. Heat from a vertically stacked die couples into its neighbors. Solder joints carry mechanical stress from drop and vibration. Co-packaged optics add an optical layer that has to be co-simulated with the thermal and electrical layers in the same run. The toolchain can solve all of that. It just cannot solve it fast enough for the iteration rate a chiplet program expects.

The practical workaround, where teams have one, is to drop fidelity. A coarse pass screens the design space, and a fine pass runs only on the survivors. That trade is reasonable, but it pushes error into the screen step, and the screen step is exactly where program decisions get made. Faster solvers, surrogate models that front-load the coarse pass, and tighter parameter sweeps are all on the table. None of them are mature enough yet to take the days out of a full multi-physics run on a 3D stack with co-packaged optics.

Adoption framing, meanwhile, treats chiplets as established rather than emerging. The IDTechEx "Chiplet Technology 2025-2035" report (paywalled) is the source most often cited for the "mainstream across data centers, AI, telecom, automotive" line. The specific market-share and forecast figures behind that framing are not independently verifiable from the open material, so the claim should be read as IDTechEx's adoption view, not a market consensus.

The Semiconductor Engineering piece is single-author trade-press commentary, not original reporting, and the hydrated text carries no on-record quotes. That does not weaken the technical argument; it does mean the bottleneck thesis is a point of view, supported by the MFIT preprint, and worth weighing against the EDA vendor (Cadence, Synopsys, Siemens EDA) and standards-body (UCIe, BoW, AIB) positions on the gap.

The forward question is operational. If the toolchain can already analyze the physics, where does the industry take the cost out of the run? For a design lead, the version of the question to put in front of an EDA vendor is simpler: what is the multi-physics sim-loop cycle time today, and what is it on the next release? For a program manager, the version is whether schedule risk now sits in compute time, not in fab capacity or tool maturity.