Chip interconnect startup Kandou AI raises $225M in funding - SiliconANGLE

When the two biggest sellers of serializer-deserializer intellectual property write checks to a company that uses their IP to build chips, one of two things is happening: they think the technology is real enough to want exposure, or they are buying a closer look at an eventual acquisition. Either way, it is not what you expect from passive investors.

Kandou AI, a chip interconnect startup founded as an École Polytechnique Fédérale de Lausanne (EPFL) spinoff in 2011, raised $225 million in an oversubscribed Series A, the company announced this week. The round was led by Maverick Silicon, with participation from SoftBank, Synopsys, Cadence Design Systems, and Alchip Technologies. Bloomberg first reported the raise, citing a valuation of approximately $400 million, according to reporter Nino Paoli. The Bloomberg article is paywalled; the primary source is the company press release.

Synopsys and Cadence are not typical venture investors. Both companies sell the SerDes IP building blocks that competitors use to design high-speed links. Synopsys DesignWare and Cadence IP cores are in the foundational layer of nearly every high-speed chip going into AI infrastructure today. Their participation here means they believe Kandou's copper multiple-input, multiple-output (MIMO) approach is either complementary to that stack or good enough to matter. This is the buried angle in a funding round that looks, on the surface, like another AI infrastructure check.

The technology comes from Amin Shokrollahi, an IEEE Fellow and Bell Labs veteran with over 30,000 Google Scholar citations, who founded Kandou on a mathematical insight about copper signaling. According to SemiWiki's history of the company, Shokrollahi discovered "chord signaling" while working on DSL line coding — spreading data signals across multiple wires the way bees collaborate in a hive ("Kandou" means beehive in Farsi). The first prototype ran at 6.25 gigabits per second per wire over a 10-centimeter PCB trace and was presented at ISSCC in 2014. The company has been at this for 15 years.

The core claim, outlined in a Synopsys blog post co-published with Kandou the day before the funding announcement, is that existing copper links are leaving most of their capacity unused. The Shannon limit — the theoretical maximum information rate for a communication channel — shows 8 to 20 times more capacity available in copper links than what conventional PAM4 signaling currently exploits. That is not Kandou's marketing language; that is information theory. The question is whether the practical analog engineering required to unlock it holds up at AI cluster scale.

Shokrollahi, now chief technology officer after handing the CEO role to Srujan Linga in April 2025, put it plainly in that blog post: the constraint is not the wire, it is what the industry has historically asked of the wire. Linga added that AI cluster architectures are hitting a "memory wall" — bandwidth to memory and between accelerators is throttling utilization of the compute already in the rack.

Linga is an unusual choice to run a deep-tech interconnect startup. He spent 16 years at Goldman Sachs as a managing director and global head of structured credit financing. He then served as Senior Investment and Financial Structuring Director at CHIPS for America, the U.S. Department of Commerce program overseeing the $39 billion semiconductor manufacturing investment created by the CHIPS and Science Act. That job put him at the table for decisions about which semiconductor projects got federal backing. He joined Kandou after that. The April 2025 leadership announcement is factual; the implications are worth watching.

Kandou is not new to shipping hardware. The company's Matterhorn USB4 retimer chip was deployed in five of the top six PC original equipment manufacturers, according to a June 2022 GlobeNewswire release, with more than 28 million chips worldwide according to Kandou's own 2025 materials. Bloomberg characterized the current strategy as a pivot from consumer hardware to AI infrastructure — that framing is accurate. They had a real consumer business and chose to move it. The $225 million is the bet that AI infrastructure is the bigger market.

The specific product focus coming out of this raise is on 448G copper links and beyond — the next generation of SerDes bandwidth for AI rack interconnect. The company claims 12 times cost reduction for AI inference systems and 2.5 times capital expenditure reduction for in-memory database deployments, figures from the company press release that have not been independently verified and should be read as company claims.

The competitive landscape is well-funded and entrenched. According to TrendForce reporting from March 2026, Broadcom's Tomahawk 6 switch chip ships with 100G and 200G SerDes manufactured on TSMC 3-nanometer process, with co-packaged optics support. Marvell Technology leads on PCIe SerDes cadence. MediaTek broke into Google's tensor processing unit supply chain with 224G SerDes. Nvidia is opening NVLink Fusion SerDes IP to partners. The incumbents are not asleep.

Kandou's copper MIMO approach is a different bet than co-packaged optics or exotic photonic interconnect. It is a bet that the installed base of copper — already in every rack, already proven at scale — can carry significantly more data than it currently does, without retooling the physical layer. If the Shannon limit math translates to production silicon the way Shokrollahi's research program says it should, that is a defensible position. If it does not, $225 million buys a lot of runway to find out.

What the company has not disclosed: named hyperscale customers, prior funding history, and whether the Hyderabad design center mentioned in the press release is a new facility or an expansion. Those are the threads worth pulling at the next funding milestone.