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HBM is the stacked DRAM that feeds AI chips. Samsung's Sept. 1 chip industry keynote in Taipei splits the roadmap: an HBM5 spec bump for 2028 and a post 2029 design that puts memory directly on the processor.
Samsung's next AI memory play splits into two bets, and aggregator coverage has been running the larger number under the wrong headline. The first is a 2028 spec bump. The second is a post-2029 architectural move that puts memory directly on top of the AI processor, and the 8x figure belongs to the second, not the first.
AI accelerators are fed by HBM, the stacked DRAM dies placed next to the processor on the same package. As model sizes have grown, the bandwidth between accelerator and memory has become the rate-limiting step for many AI workloads, a constraint engineers call the memory wall. Samsung's Sept. 1 keynote at SEMICON Taiwan, delivered by corporate VP Jangseok Choi at the Memory Executive Summit in Taipei, treats that wall as a layout problem, not just a speed problem.
The near-term step is HBM5. Samsung's roadmap targets twice the performance of HBM4E and 20% higher performance per watt, with a 20% reduction in thermal resistance. The base die, the logic layer that the DRAM stacks sit on, moves from Samsung's 4nm process to a 2nm node. Samsung is preparing 12-, 16-, and 20-Hi stacks for HBM5, with mass production targeted around 2028.
The longer-arc move is zHBM, and it carries the bigger number. zHBM stacks the memory directly on top of the processor die, instead of beside it on the package, which is the architectural shift. Samsung targets 8x the performance of HBM4E and 3x the performance per watt, with a 75% to 90% reduction in thermal resistance, and says zHBM arrives after 2029.
The framing came from Samsung's own CUBE strategy, Capacity, Utilization, Bandwidth, Efficiency, with vertical 3D integration as the central move. Choi put it directly: "We will no longer be constrained by the printed circuit board area. By expanding vertically, we can increase memory capacity without increasing the board footprint."
On Aug. 10, Samsung reported roughly 80% yield on HBM4 and said it was speeding up HBM4E. That yield, the share of usable chips per wafer, is the gate a 2nm base die and 20-Hi stack have to clear before 2028. HBM4 and HBM4E are the predecessors HBM5 inherits its process from, and the August datapoint is the most recent public signal that Samsung's HBM line is hitting the manufacturing maturity its roadmap depends on.
A third piece of the roadmap, zNAND-O, is targeted at a different buyer. Samsung aims for 10x the bit density of DRAM at NAND scale, with 7x the read bandwidth and power efficiency of conventional NAND, and sampling in 2028. TechTimes reports the use case is smartphones, not GPU servers, a tier of memory the LLM-era data center is not directly waiting on. Samsung's own tech blog frames it as part of the same CUBE push, but the audience is consumer devices, not training clusters.
HBM is already the hottest part of an AI accelerator package. The 75% to 90% thermal resistance reduction Samsung cites for zHBM is a target, not a shipped benchmark. Vertical stacking relocates the cooling problem rather than removing it, and no public data shows whether Samsung's packaging can keep a stacked-on-processor die within accelerator thermal limits. What will tell whether Samsung can hold the 2028 HBM5 date is HBM4E yield, and that ramp is still in progress.
HBM4E production volume over the next two quarters is the figure worth watching. The HBM4E ramp now underway is the credibility test for the rest of the roadmap.