RISC-V's New Server Standard Gives the Open Chip Architecture a Real Shot at the Data Center

Last month in Bologna, the RISC-V Server Platform Specification 1.0 was officially ratified. RISC-V is an open-standard instruction set for processors, a free, royalty-free counterpart to the proprietary chip architectures that dominate today's servers. Spec 1.0 standardizes the boot and runtime layer: UEFI firmware and ACPI 6.6 power management, the same plumbing an off-the-shelf operating system already speaks on Intel and Arm hardware. That is the structural change hiding behind the keynote rhetoric.

The ratification was the headline from RISC-V Summit Europe 2026, and the moment that turned an architectural movement into a platform vendors can plan against. Built on the RVA23 profile, which RISC-V International calls a major milestone for general-purpose and high-performance compute, the spec turns "yet another ISA" into a target.

RVA23 does not specify a chip. It specifies the contract a chip must keep. The profile PDF describes which instruction-set features and privileged-mode behaviors a server-class RISC-V CPU has to expose. Ubuntu's engineering write-up of RVA23 explains why that distinction matters: distros, hypervisors, and firmware need a stable target so they do not have to ship a different binary tree for every vendor's interpretation. Rivos's RVA23 explainer makes the same point for HPC. A profile collapses that variability into one name the procurement office can write into a tender.

Andrea Gallo opened the Bologna summit with a flat declaration: "RISC-V is now." That is the kind of line that usually reads as marketing. In this case, EE Times' on-site report backs it up with a concrete deliverable. Spec 1.0 is the artifact that earns the line.

Krste Asanović, chief architect at SiFive, gave a "State of the Union" keynote presenting the architecture as moving from embedded controllers into HPC and enterprise servers. He told EE Times by email that RISC-V is "closely working with" hyperscalers and data center suppliers on next-generation processors, citing flexibility over incumbent architectures as the draw. That is a forward-looking statement, not a shipping claim. The interest is real; the deployments are not yet on the page.

The named companies matter because they define the addressable market. Meta, Google, Nvidia, Qualcomm, and Alibaba are cited as adding RISC-V to their portfolios, language that puts RISC-V on the same planning whiteboard as Arm and x86, not on the embedded controller shelf. Server procurement is a strategic lock-in point for governments and large enterprises. A credible third option changes that leverage, even if no one is replacing Intel's installed base this quarter.

The Bologna program itself showed the breadth of the bet. Developer workshops were sold out, with roughly 120 engineers working through hands-on debugging and advanced hardware design. Sessions covered edge neural network deployment and high-performance processors in space, an active discussion rather than a deployed fleet, but a marker that the ecosystem is talking about RISC-V outside the microcontroller bucket.

The critical reading survives the marketing. RVA23 and Spec 1.0 are foundations, not products. The hyperscaler language is "closely working with" and "investing in," not "shipping in production." Rivos, one of the vendors most exposed to RISC-V's enterprise story, is still pitching the architecture's possibilities rather than naming reference customers. Watch three things over the next 18 to 24 months: the first RVA23-conformant servers shipping in volume; the first major distro or hypervisor declaring RVA23 a tier-1 target; and the first hyperscaler disclosing a deployment rather than an investment. Until then, the Bologna ratification is the contract. Silicon has to sign it.