HWBRIEF
Washington State University and University of Wisconsin–Madison's ReVolt uses a learned power model to predict voltage swings per chiplet—small silicon tiles connected side by side inside a 2.
Researchers from Washington State University and University of Wisconsin–Madison have proposed ReVolt, a framework targeting voltage droop, the brief millivolt-scale sags in a chip's supply rail, inside 2.5D multi-chiplet AI accelerators paired with processing-in-memory (PIM) tiles. In those stacks, shifting inference workloads push the shared power-delivery network (PDN) below its voltage margin, corrupting results or forcing throttling.
ReVolt treats the PDN as a runtime control problem. An LSTM-based surrogate model, a recurrent neural network trained offline on power-delivery simulations, predicts each chiplet's supply-voltage trajectory. Operation-unit (OU) size, which sets how much parallel work each chiplet takes, becomes the control knob. When the predictor sees an incipient droop, ReVolt resizes the OU to shed current before the rail sags, then re-expands it once the load settles.
Sharma, Kanani, Sun, Doppa, Ogras, and Pande report an average 76x reduction in energy-delay product (EDP), the standard research metric that multiplies runtime by energy use, against fixed and dynamic OU baselines, with no loss in inference accuracy.
The 76x figure is a research claim, not a shipping product. ReVolt is a simulation-and-experimental outcome from one group against prior operation-unit schemes in the same setup, not a foundry tape-out or hyperscaler adoption signal. As AI accelerators stack more memory next to compute, predictive PDN control is moving from a margin to over-provision toward a first-class design lever.