Quantum Error Correction Just Got 9.25x Faster on NVIDIA Hardware

Alice & Bob wants to build quantum error correction faster. A partnership with NVIDIA, announced at GTC 2026 last week, shows the company running its Elevator Codes simulations on NVIDIA's CUDA-Q platform and achieving a 9.25x speedup in decoding time — from 18 hours and 2 minutes on a CPU-based implementation to 1 hour and 57 minutes on a GH200 Grace Hopper system, across 100,000 simulated shots.

The benchmark compares an NVIDIA GH200 against an AMD Ryzen 9 9950X 16-core CPU. Alice & Bob, which specializes in cat qubits — a qubit modality where one error type (bit-flips) is passively suppressed by hardware design — says the GPU-accelerated approach maintains identical logical error performance with no decoding accuracy degradation. The result was presented by Sam Stanwyck, Group Product Manager for Quantum Computing at NVIDIA, at a GTC session on March 16.

What Alice & Bob actually announced: a faster way to simulate error correction for their specific hardware. That is not nothing. Quantum error correction is the bottleneck between where quantum hardware is today and where it needs to be for useful computation. The decoding step — interpreting syndrome measurements to detect and correct errors in real time — is classically intensive and becomes more so as processors scale. If you can simulate QEC cycles faster, you can iterate on fault-tolerant architectures faster.

The architecture in question is Elevator Codes, which Alice & Bob described in a preprint published in January. The scheme uses a concatenation of two classical codes: an inner repetition code for phase-flip errors (which cat qubits don't suppress passively) and an outer high-rate bit-flip code, implemented at the logical level, that the company says reduces qubit overhead compared to previous approaches. The company claims 10,000x lower logical error rates using 3x more qubits relative to its standard repetition code architecture, based on the preprint results. The arXiv preprint has not yet been peer-reviewed.

The deeper context: Alice & Bob's bet on cat qubits is that the hardware overhead for fault tolerance can be reduced if your qubit modality already suppresses one error type passively. Cat qubits achieve extremely long bit-flip lifetimes — the company says its measured idle bit-flip lifetimes are now "in hours' territory," millions of times longer than competing superconducting qubit technologies. The remaining problem is phase-flips, which don't benefit from the same passive protection. Elevator Codes is the company's answer: actively correct bit-flips in addition to phase-flips, on the same hardware, without proportional qubit overhead.

The partnership with NVIDIA goes back to June 2025, when the companies integrated CUDA-Q into Dynamiqs, Alice & Bob's QPU simulation library. The GTC announcement extends that integration into production QEC simulation workloads. Tim Costa, NVIDIA's Senior Director of CAE, Quantum and CUDA-X, called it a step toward "seamless integration between quantum hardware and accelerated computing."

Whether the 9.25x speedup matters for the timeline to useful quantum computing depends on how you frame the problem. Faster simulation accelerates the design cycle. It does not accelerate the runtime of actual quantum algorithms. For building large-scale fault-tolerant machines, that is genuinely useful. For running Shor's algorithm on real hardware today, it changes nothing.

Alice & Bob is not alone in this infrastructure play. NVIDIA's CUDA-Q has also been integrated with IQM and other quantum hardware providers. The competitive question is whether the classical co-processing layer — GPUs handling decoding, calibration, and control tasks — becomes a differentiator in its own right, or whether it remains support infrastructure for the quantum hardware that others build. NVIDIA is clearly hoping for the former.

Founded in 2020, Alice & Bob has raised €130 million and employs more than 200 people across Paris and Boston. The company is advised by Nobel Prize-winning researchers and its cat qubit technology was developed by its founders. It has not yet shipped a fault-tolerant quantum computer.

The Elevator Codes preprint is available on arXiv (2601.10786). The CUDA-Q integration result was announced via EIN Presswire on March 16, 2026, and covered by Quantum Computing Report.