Quantum computing's wiring problem gets a credible lab-scale fix

For most of quantum computing's history, every operation on a chip colder than deep space has required a round trip to a room-temperature control rack. Coax cables threaded through a cryostat carried timing pulses to the qubits, then carried measurement signals back out. The architecture is fine for a handful of qubits. It does not scale.

A Nature paper published July 29 by HRL Laboratories replaces that round trip with on-cryostat control. The work is the first peer-reviewed demonstration of an 18-qubit silicon spin chip that runs its own error checks without a warm computer in the loop, and it does so on a 200 millimeter semiconductor production line.

HRL, a research lab jointly owned by Boeing and General Motors, is not a household name in computing. The Malibu lab has been one of the more persistent U.S. groups working on silicon spin qubits, the type of quantum bit that stores information in the spin of a single electron trapped in a quantum dot. The attraction is that the same foundry tools used to build commercial microprocessors can build the qubits, so a path to mass production is plausible in principle. The problem has always been the wiring.

The paper describes three engineering pieces that together address that bottleneck. The first is a custom controller chip that lives at 4 kelvin, the temperature of liquid helium, inside the same cryostat as the qubits. Built in 130 nanometer radio-frequency CMOS, a chip process node used in cell phone parts rather than exotic hardware, the controller contains 70 million transistors and draws under 3.5 watts. HRL reports that the chip routes 150 time-varying control waveforms to the qubits and dumps less than 10 microwatts of heat into the colder stage of the cryostat, the part where the qubits themselves sit at around 150 millikelvin. That low thermal load is the whole point. Earlier attempts to push control into the cold stage failed because the controller's own waste heat drowned the qubits in noise.

The second piece is the interconnect: a flat ribbon cable, 296 traces wide, made of superconducting niobium laid on a flexible polyimide plastic sheet. It bridges the 4 kelvin controller to the sub-kelvin qubits, carrying the control signals without the resistive losses of the metal cables used in older systems. Because the traces are superconducting, they do not generate the heat that scales with cable length, which is the constraint that has kept quantum systems small.

The third piece is the qubit wafer itself, built on 200 millimeter disks of silicon-germanium enriched so that almost no silicon-29 atoms are present. Silicon-29 is the isotope whose nuclear spin creates noise in qubits. HRL fabricates a 54-quantum-dot array on each chip and configures it for up to 18 "exchange-only" qubits, a specific silicon spin encoding that lets two-qubit gates run on neighboring dots with minimal control overhead.

The benchmarks are the part the field will scrutinize. The team reports an average single-qubit gate error of 1.7×10⁻⁴, a two-qubit CNOT error of 3.5×10⁻³, and a lowest reproducible two-qubit error of 9×10⁻⁴. Charge noise, a long-standing problem for quantum dots, is reduced about tenfold compared with older designs, with charge noise now contributing only about 0.02% of the total gate error.

The chip also runs a quantum error-detection code called a [[4,2,2]] code, which uses six physical qubits to protect two logical ones, and HRL reports a 95% post-selected fidelity on the two logical qubits across three rounds of error checks. On distance-3 and distance-5 repetition codes, or progressively longer error-detection routines, the suppression factor between the two, Λ5/3, is 4.7. That is the right sign, but a long way from the thresholds needed for fault-tolerant operation. An arXiv preprint of the same paper is available for readers who want the full data set.

The honest read is that 18 qubits, a single paper, and a Λ5/3 of 4.7 are a proof of engineering concept, not a quantum computer that can do useful work. The platform still has to scale to thousands of qubits before it can run the algorithms the field cares about, and the cryostat problem gets harder at every step, not easier. The Quantum Insider and other trade publications have re-summarized the HRL release; the Nature paper is the authoritative source.

What the result does change is the kind of problem the field is now solving. Until this week, the wiring and thermal load that connect a quantum chip to its controller looked like a physics constraint, the kind that needed a different qubit to bypass. HRL's demonstration is a reminder that on silicon, the constraint is engineering, and the engineering sits on a 200 millimeter line.