Inside the federally funded NORDTECH consortium — a CHIPS Act microelectronics hub led by NY CREATES — SEEQC, a superconducting quantum hardware company, will build a near absolute zero test rig and a standardized quantum design kit for Cadence, the EDA software firm, targeting…
For two decades, superconducting quantum processors have been hand-built in university cleanrooms, in small batches with recipes that do not always survive being repeated. A federally funded consortium now wants to move that work onto the same 300mm silicon production lines that make the processors in laptops and phones, and the engineering bets behind that move explain why "scaling quantum hardware" is a manufacturing problem, not a physics one.
The project runs through NORDTECH, a Microelectronics Commons hub created under the CHIPS and Science Act and led by NY CREATES, the Albany-based nonprofit that operates the state's 300mm fab. The hub's founding governance members include the University at Albany's College of Nanoscale Science and Engineering, Cornell, Rensselaer Polytechnic Institute, and IBM. NORDTECH's project partners for this effort include Cornell, Princeton, NYU, Syracuse, the Air Force Research Laboratory, and both Quantum Circuits and D-Wave, two companies in the superconducting hardware space whose division of labor within the program is not described in the announcement.
The headline engineering question is whether superconducting qubits can be fabricated with the yield, repeatability, and materials control that 300mm silicon lines demand. Superconducting qubits are tiny circuits, often built from layered thin films on a silicon substrate, that only conduct electricity without resistance when chilled to near absolute zero. The main failure modes are well known in the field: dielectric loss, energy that leaks out of the qubit into the materials around it, and defects in those materials that absorb and re-emit energy unpredictably. Both shorten the time a qubit can hold its quantum state, a property called coherence.
The consortium's materials bet is on the refractory metals tantalum and tantalum nitride, two compounds already used in conventional chip wiring and now being optimized inside the 300mm line. Tantalum nitride is hard, conductive, and stable at the high temperatures used in semiconductor processing. Tantalum is a dense, high-melting-point metal that, in thin films, has shown some of the lowest dielectric loss measured in superconducting qubit circuits. Suppressing dielectric loss is the main lever for raising baseline qubit coherence, which is why the materials choice is the engineering centerpiece of the program.
SEEQC's announced role in the program sits at the test-and-design end of that effort. The company says it will deliver a high-throughput cryogenic qubit evaluation and characterization platform, in effect a near-absolute-zero measurement rig that can test many candidate chips quickly and feed results back to the fab line so recipes can be tuned. SEEQC also says it will deliver one of the first standardized quantum Process Design Kits integrated into the Cadence EDA ecosystem. A Process Design Kit is the standardized set of design rules, device models, and component libraries that chip designers use to lay out circuits; a quantum PDK that fits into mainstream EDA tools is a bet that superconducting hardware design can become reproducible and shareable the way conventional chip design became decades ago. The kit is designed to be compatible with SEEQC's own digital Single Flux Quantum control architecture, a superconducting logic family the company is pitching for hybrid multi-tier quantum systems that pair processors with their control electronics on the same chip.
That last piece is also a bet. SEEQC's PDK and SFQ control story is a company-asserted product strategy, and the press release announcing it, covered same day by Quantum Computing Report, frames SEEQC's role with the superlative-heavy language ("first standardized quantum PDK in the Cadence ecosystem") that quantum hardware announcements usually carry. SEEQC is also a subcontractor, and the company has not disclosed its individual funding share within the hub. The $25 million-plus figure attached to NORDTECH in public summaries is hub-level, covering multiple projects across the program.
The honest framing is that the consortium is buying down specific risks. The 300mm line exists, the materials are known, and the characterization problem is well-defined. What is unproven is whether superconducting qubits can hit industrial yield on a line that was designed for transistors, not for circuits that have to survive being cooled within a hair of absolute zero, and whether a standardized quantum PDK plus cryogenic feedback loop is enough to close that gap.
What to watch next is concrete. The NORDTECH project will need to publish yield and coherence data from 300mm-fab qubit wafers, and the Cadence-integrated quantum PDK will need to land with at least one external design team using it for a real chip, not a demo. Until those checkpoints land, the program is a credible engineering bet on a known bottleneck, and the only honest reading is that superconducting quantum hardware is moving from cleanroom to fab slowly, on a line that may or may not learn to make these chips at scale.