Its new AI250 accelerator uses a near memory design called High Bandwidth Connect, or HBC, instead of high bandwidth memory — the DRAM stacks priced and produced almost entirely by SK hynix, Samsung, and Micron. The bet: data center inference workloads don't need it.
Qualcomm has spent more than two decades putting inference silicon into the battery- and thermally-constrained guts of a phone. Its pitch for the data center, the AI250 accelerator it unveiled in late October 2025, leans on that lineage. Instead of pairing its Hexagon neural processor with high-bandwidth memory, the DRAM stacks Nvidia's H100 and B100 depend on for generative AI training, Qualcomm routes data through a near-memory architecture called High Bandwidth Connect, or HBC, that places memory channels on the same package as the logic die. The bet is that the AI compute market inside server racks is splitting in two, and Qualcomm is aiming at the half high-bandwidth memory was not designed to serve.
That architectural choice matters because high-bandwidth memory is a strategic chokepoint, not just an input cost. SK hynix, Samsung, and Micron are the only three vendors producing HBM at scale. Spot prices for the latest HBM3e generation have run well above standard DRAM contract pricing, and the largest hyperscalers lock up most of the available capacity through long-term agreements. Any chip designer who wants to match Nvidia's per-accelerator memory bandwidth has to compete for the same constrained input, a fact that defines the field of credible Nvidia rivals more than any headline benchmark (technical competitive analysis).
The through line is the Hexagon lineage. Qualcomm's data center product page pitches the AI200 and AI250 as inference accelerators, sitting inside a broader "Dragonfly" portfolio the company positioned in trade press for what it calls the agentic AI era, systems where many smaller models run in coordinated loops rather than one large model returning single answers. The NPU IP at the heart of the parts is the same silicon already shipping in hundreds of millions of Qualcomm-powered phones, designed from the start for inference at low power.
Data-center inference has different scale but similar shape to phone inference: large volumes of relatively small reads against model weights. High-bandwidth memory is engineered for the opposite pattern, dense matrix math against activations during training. Qualcomm's near-memory design is a bet that feeding a Hexagon-class NPU at competitive throughput does not require HBM at all, and that the inference-first customers, hyperscalers, automotive, and edge-AI deployments, buy on per-token economics rather than peak bandwidth.
This is why Qualcomm data center chief Durga Malladi chose a midtown Manhattan conference room, not a launch stage, to demonstrate a DRAM-on-logic-die stack to Nikkei in late October 2025. The point of the demo was the memory, not the silicon: showing that placing DRAM directly on the package could deliver competitive bandwidth for inference at a fraction of the high-bandwidth-memory bill of materials. Market reaction caught the architectural contrast, too. CNBC reported Qualcomm's stock jumped roughly 11% on the AI200 and AI250 announcement, framed as direct competition to Nvidia and AMD in the inference accelerator market.
The same engineering logic opens a second door. Tom's Hardware reported Qualcomm is preparing China-specific data-center and Dragonfly parts designed to clear US export limits, and CEO Cristiano Amon told Nikkei the full data center product range will be offered to Chinese customers, a market Nvidia's most advanced accelerators are largely excluded from. A near-memory architecture reduces dependence on an export-controlled component, even if the capacity question is not eliminated (Nikkei interview).
The wire framing of the launch, "Qualcomm takes on Nvidia," is the wrong read. The comparison that matters is in mechanism terms: can Qualcomm's combination of an inference-tuned NPU and an HBC memory subsystem outperform Nvidia's GPU plus high-bandwidth-memory stack on per-token inference cost, while staying inside the power and thermal envelope of an air-cooled rack (mechanism analysis)? The honest answer as of mid-2026 is that no independent hyperscaler or large enterprise customer has publicly benchmarked the part under sustained production load. The closest analogues are Apple's data-center silicon and Google's TPUs. Both took years from announcement to material deployment share, and the cost of that runway is rarely priced into a launch-day stock move.
The reason to watch this is the memory supply curve, not the rivalry. If Qualcomm's HBC design works in production at scale, it puts pressure on Nvidia in two places at once: inference unit economics, and the assumption that every serious AI accelerator has to ride the high-bandwidth-memory supply curve. If it does not work under sustained inference load, the AI250 joins a long list of credible designs that did not translate to production. Either outcome makes memory architecture, not corporate rivalry, the actual story.
Watch next: independent benchmarks comparing AI250 inference throughput per dollar against an Nvidia H100 or B100-class part running the same models under sustained load, and any disclosure of an anchor hyperscaler, automotive, or edge-AI customer under production deployment rather than pilot.