The Pohang lab's process hit roughly 4x today's best high bandwidth memory (HBM) density. The result is research stage, but it targets the AI memory wall. The team bonds each die in place as it is transferred onto the stack, rather than after.
Researchers at Pohang University of Science and Technology (POSTECH) have stacked more than ten ultrathin semiconductor dies into a single high-bandwidth memory (HBM) package by bonding them in place during the transfer-print step, rather than after. The reported result is roughly four times the memory density of the most advanced HBM chips shipping today. An HBM stack sits next to an AI accelerator and feeds it data, and it has been the binding bottleneck for training and running the largest models, per SemiAnalysis on the HBM roadmap.
The step that matters is the bond moment: it happens during the transfer, not after the die is placed. Conventional stacking lifts each die with a pick-and-place tool, aligns it, and welds the layers afterwards, which works until the dies get thin enough that handling cracks them. POSTECH's team used a transfer-print process that picks up dies roughly one-fifth the thickness of a human hair and tacks them down with an in-situ bonding step before releasing the carrier. The combined process is published in Results in Engineering, and the POSTECH press release frames it as a route to "semiconductors in the era of skyscrapers."
In HBM, the limiting factor is not the memory cell but how many layers fit into the package next to the GPU before it gets too thick. Halving each die's thickness turns a five-layer stack into a ten- or twenty-layer one at the same total height. The blocker has been that dies below roughly 50 micrometers crack under conventional handling. Bonding during the transfer removes the worst of those moments. The industry's scramble on this point runs in parallel: IEEE Spectrum's look at lateral chip stacking covers the complementary path of spreading memory sideways, and Korean press reporting has confirmed the result independently (Seoul Economic Daily).
The "4x" number depends on which HBM generation is the reference, and the paper does not name it. HBM4 is the latest shipping generation; HBM5 is on the roadmap with new packaging constraints, and the POSTECH process has not been characterized against either. Independent industry analysts, including TrendForce, Yole, and SemiAnalysis, have not weighed in on this specific technique, and the work is a lab demonstration, not a fab process. Yield, thermal behavior, and standards adoption are still ahead.
The lab's work moves the bottleneck from die thickness to bonding technique. The next checkpoint is whether another team reproduces the result or an HBM maker picks it up.