QCBRIEF
BTQ Technologies, a Canadian quantum security vendor, and ITRI, Taiwan's Industrial Technology Research Institute, say a chip built on a 28 nanometre transistor geometry does the cryptographic math inside the memory array instead of in a separate
NIST has finalized three post-quantum cryptography standards: FIPS 203, 204, and 205. The question has moved from which algorithms to use to whether real devices can run them. BTQ Technologies and ITRI say they have answered part of that question for one class of hardware accelerator: a pre-silicon "QCIM" core has been validated as functionally correct inside a TSMC 28-nanometre design environment, and can run all three NIST algorithms.
QCIM is a soft-IP compute-in-memory block: silicon that does the crypto work where data sits, instead of shuffling bits back and forth to a separate compute unit. Post-quantum algorithms carry larger keys and signatures than older schemes, and conventional crypto accelerators spend much of their time and energy on data movement. Doing the math in memory is one proposed way to attack that bottleneck. The block is built to be crypto-agile, able to switch algorithms as standards evolve.
The validation is the first technical milestone in a multi-year collaboration between BTQ and ITRI, part of a QCIM chip roadmap co-led by BTQ and ICTK Co., Ltd. The next step is module-level integration. BTQ says test chips will reach "key customers and strategic partners" by year-end, a vendor forecast rather than a confirmed shipment.
What remains unverified: independent benchmarking, any NIST submission, and quantified throughput, power, and area numbers.