Agentic inference and selective scale up have pulled the general purpose bus back into the AI stack, with CXL maturing on top and the new fabrics doing the job they were actually built for.
The headline of the AI build-out was always going to be the new fabrics. Scale-out interconnects, custom silicon-to-silicon links, optical eventually: that was the future the consensus had been building toward for years. The general-purpose bus that connected CPUs to add-in cards was supposed to become a relic, useful in the same way a USB-A port is useful on a new laptop.
That is not what is happening. According to Ed Sperling's analysis in SemiEngineering, the Peripheral Component Interconnect Express standard is absorbing more AI workload, not less, even as the protocols underneath it strain against physical limits. The story is not "PCIe won" or "PCIe died." It is that the standard has been quietly absorbed into a piece of plumbing the new fabrics were never designed to carry.
The framing matters. Treating AI as a single workload is what produces the wrong predictions. AI infrastructure has split into at least three distinct shapes, and PCIe is useful in two of them.
The first is agentic AI, the next build-out. The model that writes code, queries a database, calls a tool, and writes more code is a system of repeated, low-latency hops between a CPU host and accelerators, NICs, and storage. That kind of traffic looks much more like the old general-purpose data center than like the tightly coupled training cluster. The PCIe physical layer was already there. So was the switch and retimer ecosystem. Buying more of the same thing is easier than qualifying a new fabric for every mid-sized deployment.
The second is selective scale-up. Not every AI job needs an NVLink-class fabric or a coherent domain spanning eight accelerators. Most production inference, most enterprise fine-tuning, and most of the long tail of model serving runs on hardware that PCIe connects just fine. Sperling's read is that scale-up interconnects were built to handle the largest, most painful jobs. They were not built to replace PCIe everywhere, and they have not.
The third is the largest-scale training cluster, which is where the new fabrics actually live. Here PCIe concedes the field by design: a domain that pulls thousands of accelerators into a coherent mesh is not a problem the standard was ever sized for. The point is not that PCIe is dominant in this layer. It is that the layer is one layer. The total AI build-out is much larger, and the rest of it does not look like the biggest training run.
On top of this stack, CXL is finally doing what it was supposed to. The Compute Express Link standard sits adjacent to PCIe rather than replacing it: same physical layer, different protocol, designed to extend coherent memory and pool resources across devices. Adoption has been slow, in part because the deployment questions are still being answered in production. Who pays for pooled memory, which workloads actually benefit, which software stacks have to change: these are open questions, not solved ones. Sperling's framing is that CXL is maturing on top of the PCIe substrate rather than competing with it. That is more useful than the "CXL is killing PCIe" narrative that briefly circulated in the trade press. The two are siblings. One extends the other.
At the edge, a parallel pattern is unfolding. MIPI Alliance specifications and other compact interconnects are growing as AI moves into phones, cars, cameras, and industrial endpoints. The protocol names are less familiar, but the shape of the problem is identical. A general-purpose standard absorbs a new class of device, the most demanding workloads peel off onto a specialized fabric, and the general-purpose standard keeps expanding. The edge is to the data center what agentic inference is to training: a deployment surface that does not need a scale-out fabric and never will.
The forward model for the next two years is straightforward. PCIe will keep absorbing the AI workload that resembles classical enterprise compute. CXL will keep maturing on top of it, with the deployment questions being answered in production rather than on slides. Scale-out fabrics will keep growing inside the largest training clusters and the largest inference fleets, because that is the job they were built for. Edge protocols will keep tracking the spread of AI into devices. The mistake to avoid is treating any of these as a zero-sum contest. They are layers. The build-out is bigger than any one of them.
What to watch next: where CXL actually shows up in production at scale, which is still an open question. Whether the agentic-AI workload mix holds and pulls PCIe deeper into the stack. And how the edge protocol landscape consolidates as more endpoints ship with on-device models. The standard that was supposed to be a relic is doing the unglamorous work of moving bytes, and the new fabrics are doing the job they were designed for. Neither story is the whole story.