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TIER IV, the Japanese company behind the open Autoware self driving stack, is joining a Japan Science and Technology Agency (JST) backed University of Tokyo program to publish, as open source, the logic design (the chip's circuit blueprint) and
TIER IV, the Japanese company behind the open-source Autoware autonomous-driving software, is joining a Japan Science and Technology Agency (JST) program to design an AI chip for Level 4 driverless cars and publish the logic design and compiler as open source. The work pairs TIER IV with a University of Tokyo team led by Professor Yoshihiro Kawahara of the Graduate School of Engineering, inside the JST Next-Generation Edge AI Semiconductor R&D Program (project code JPMJES2513).
The announcement hides the part that determines whether the bet works. The fabricated silicon, the third-party IP blocks, and the verification path that turns a logic design into a chip you can buy are not part of the open release. What is open is the design layer: the register-transfer-level description of what the chip does, and the compiler and tooling that let application researchers target it. That boundary is the story.
Level 4 autonomous driving is the tier where a vehicle operates without a human driver inside a defined operating domain: a robotaxi on a mapped city district, a delivery van on a fixed loop, a truck inside a fenced port. The JST project document describes the broader ambition as a shift from a "giant single brain" to a "distributed nervous system," splitting the workload into thinking, reflex, and peripheral chips and only invoking the thinking layer when the situation demands it. TIER IV's chip is meant to be the thinking layer.
The target is a dedicated Transformer inference engine, the kind of circuit that runs the large attention-based neural networks now standard in modern driving stacks, with on-chip data reuse so the chip avoids shuttling activations back to external DRAM. Memory access is where the energy goes in AI silicon, and at the edge — in a moving car, off a battery — that energy bill is a thermal and range problem, not just a benchmark number. TIER IV positions the chip as a complement to general-purpose GPUs, not a replacement: the reflex and peripheral layers still live elsewhere, and the heavy offline training still happens in a data center.
TIER IV's role inside the program is the software-defined part. End-to-end AI in driving means a single neural network takes raw sensor input and produces motion commands, rather than a pipeline of separately trained modules for perception, tracking, and planning. That style of stack is what most modern autonomy systems are converging on, and it is what TIER IV plans to compile directly onto the new chip using the open toolchain. Autoware is the autonomy software layer the chip is being designed against, which gives the program something most open-silicon efforts do not have: a real application stack to integrate with, not just a reference benchmark.
The institutional context matters. JST is a public research funder; the project's co-research institutions are TIER IV, Keio University, and the University of Tokyo. The program also sits inside a wider push called Agile-X, a hub meant to let application researchers shape the silicon their workloads run on, rather than handing that job entirely to chip architects. The stated downstream goal is the emergence of Japanese high-value semiconductor design startups — fabless players who can commercialize inference chips for specific industries without each one rebuilding the design stack from scratch.
The credibility of the bet is not the press release. Open-source AI accelerator silicon has a thin track record outside microcontrollers; RISC-V, the OpenPower lineage, and efforts like SiPearl in Europe have moved the open-design conversation forward, but Level 4 inference has not been put through it at production scale. Publishing the logic design and compiler is a real contribution, and it is exactly the kind of move that lets smaller teams build on top of the work. It is not the same as open fabrication, and the JST document does not claim it is. The chip, the IP blocks, and the verification path remain separate questions, and the announcement does not put a date on any of them.
What changes today is that the open-source stack now has a credible claim on the design layer of Level 4 inference, with a named autonomy ecosystem underneath it. Whether that claim survives contact with a fabricated chip is the next milestone to watch.