AIBRIEF
Cadence, Siemens and Synopsys dominate that market. Nvidia says they are already wiring in its new physics simulating AI; outside benchmarks are not yet public.
Nvidia is pushing deeper into the software stack that chip companies use to design chips, a market long controlled by three vendors: Cadence, Siemens, and Synopsys. At a July keynote, the chipmaker said those companies are now wiring its new "agent" tools into their electronic-design-automation (EDA) platforms.
The package combines reworked PhysicsNeMo libraries with three new CUDA-X solvers: cuISS and cuDSS for sparse linear systems in chip and circuit simulation, and cuEST for electronic-structure theory. Synopsys's own newsroom showcased silicon-to-systems workflows with Nvidia tech this week, and Nvidia said its Vera CPU is now running EDA workloads with Cadence and Synopsys.
VP Timothy Costa called the moment a field shift: "Engineering has reached an inflection point. AI can now work with tools of physics, simulation and design." That language is the speaker's, not an outside finding, and no independent benchmark has been published. Nvidia's open-weights Nemotron 3 Ultra is also being positioned for agentic RTL coding, the step where engineers describe a chip's logic; partner ChipAgents is one of the few named users so far.
Whether "agentic engineering" describes a real workflow change or repackages AI features the big-three already ship is the open question.