Nvidia pitches Vera as a 'max single threaded' CPU for AI agent workflows where the latency between each tool using step dominates, while AMD counters with a 3.3x throughput per server rack claim and AI search startup Perplexity publicly signs on.
Nvidia is selling its 88-core Vera CPU on a claim that inverts the parallelism orthodoxy that defined AI silicon: that AI agents need faster individual cores more than they need more of them. The chip, the CPU half of the Vera Rubin platform Nvidia announced in May, is being positioned as a "max single-threaded CPU at scale" for the sequential, branchy workflows that distinguish agentic AI from batch inference.
Agentic AI workloads look different from the batch inference pipelines most accelerators were tuned for. An AI agent that interleaves web search, code execution, retrieval against a database, and final answer synthesis does not consume cores in parallel; it consumes them one step at a time, waiting on each tool result before deciding the next call. Wide-core, low-clock designs can keep the silicon busy; they still leave the agent waiting. Nvidia's developer blog frames the design choice as a deliberate trade: latency per agent step and tool-call throughput per watt, rather than aggregate throughput on training-style benchmarks.
That argument underpins the Vera architecture Nvidia disclosed: a single 88-core Arm-based SKU built around the Olympus core. Jensen Huang has said the company expects "billions of dollars" from this one configuration. Phoronix tests show the Olympus core already posts competitive single-thread numbers against Intel Xeon and AMD Epyc chips, which is the relevant axis for Nvidia's pitch even if it is a narrow slice of the CPU benchmark world. The chip is meant to ship as a paired CPU to Rubin GPUs inside the Vera Rubin platform, not as a standalone server CPU competing for general-purpose workloads.
AMD disagrees on the metric. Tom's Hardware reports AMD is claiming a 3.3x advantage in rack-level throughput at 100 kilowatts for agentic workloads. The methodology is not published, so the figure is best read as a competitor counter-narrative rather than a head-to-head refutation. The substantive dispute is over what "throughput" should mean for agent workloads: per-watt step latency, agents-served-per-second per rack, or end-to-end task completion rate.
The architecture Nvidia is betting on does not stop at Olympus. Next comes Rigel, an Arm v9.2 core HPCWire says will appear in the Rosa CPU when Nvidia moves past the current Vera generation. Nvidia describes Rigel as improving instruction delivery, expanding L2 cache, and tightening memory handling on the same silicon class, with Phoronix's coverage adding detail on the architectural changes. The stated goal is higher single-core performance than Olympus, not more cores per socket.
One named customer has surfaced publicly: Perplexity. The AI search company called Vera a "dead-on fit" for its agentic inference stack, citing the latency-sensitive tool-call loops its own systems run every day. A single named customer is an adoption signal rather than a benchmark sweep: useful evidence that the bet has at least one production fit, weaker evidence that it generalizes across the broader agent platform market.
The architectural bet turns on a testable claim: that agent step latency, not batch throughput, is the right input to optimize for AI agent infrastructure. If the thesis holds, the CPU shape of 2025, with its dozens of modest cores per socket, looks like the wrong answer for a workload class that barely existed at meaningful scale two years ago. Huang has already telegraphed the magnitude: he has said Nvidia expects "billions of dollars" from the single 88-core SKU alone, positioning Vera as a meaningful entry into the CPU market Nvidia has historically left to Intel and AMD. If the thesis does not hold, future agent benchmarks that punish per-core latency will shift the market back toward wider silicon and leave Vera as a niche.
The next milestone is Rigel-based Rosa silicon. The watch item is independent benchmarking on full agent loops, not single-core Geekbench scores, that will decide whether "max single-threaded at scale" is a real architectural break or a slogan that happens to line up with one named customer's stack.