Nvidia Readies CUDA for RISC-V, With a Long List of Demands

Nvidia is preparing to extend CUDA, its GPU programming platform, beyond x86 and Arm to RISC-V. At Hot Chips 2026, the company spelled out, in detail, what a server-grade RISC-V host has to prove before its GPUs will feed from one.

The baseline, according to a Chips and Cheese recap of Nvidia's talk, is the RVA23 profile and the RISC-V Server SoC specification. On top of that, Nvidia requires reliability, availability, and serviceability (RAS) features, a dedicated security processor, and vector extensions with predication so CUDA can avoid branches. PCIe coherency is a hard ask: without it, CPU caches and direct-memory-access (DMA) transfers can disagree about memory ordering, a hazard Nvidia considers standard for any server CPU.

The last obvious blocker, ACPI (the hardware configuration and power-management standard), was added for RISC-V by the UEFI forum in 2025 and folded into the Boot and Runtime Services specification, ratified the same year.

Nvidia's stated reason for the long list: avoid a "lowest common denominator" CUDA build that cannot use performance extensions not guaranteed on compliant hardware. A partial-spec RISC-V host could still get a stripped-down CUDA path; full performance requires the full checklist.