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Nvidia says its custom AI memory chip beats the next industry standard on bandwidth and power, but access is locked behind its own interconnect program and Amazon's chip unit is the only named partner.
Nvidia announced a faster, more power-efficient memory chip for AI accelerators on August 26 and locked the design behind its own proprietary interconnect program. The performance numbers are real, but the access question is the bigger one: as of launch, only Amazon's chip unit is publicly in.
The chip is called NVHBM, short for Nvidia High-Bandwidth Memory, and it is the company's first custom design for the stacked DRAM that sits next to AI training and inference accelerators. Nvidia says NVHBM delivers up to 30% more memory bandwidth per stack, 15% lower HBM power consumption, and up to 25% more usable area on the accelerator die compared with the next industry standard, HBM4E.
Those numbers come with a catch that the marketing glosses over. HBM4E, the standard Nvidia is comparing against, is still in the sampling stage, with volume shipments not expected until sometime in 2027. Until real HBM4E parts ship in quantity, no one outside Nvidia's lab can verify the 30/15/25 figures independently.
The architectural change that makes those numbers possible is the part Nvidia talks about least. A high-bandwidth memory module is a 3D stack of DRAM layers sitting on a piece of silicon called the base die, which acts as the translator between the DRAM and the rest of the accelerator. On standard HBM, that translator lives on the accelerator die itself. NVHBM moves it onto the base die inside the memory stack, swapping the JEDEC-standardized wide parallel bus for a narrower, serialized die-to-die link that Nvidia designs and the memory makers build. Nvidia's technical blog claims up to a 67% reduction in interface and support area versus the HBM4E standard as a result.
That move frees up accelerator area for more compute, and it puts Nvidia in the middle of every conversation between memory makers and AI chip designers. The trade-off is that NVHBM is gated behind NVLink Fusion, Nvidia's proprietary interconnect program that already decides who can plug into Nvidia's AI platform at all. The only named partner so far is Amazon's Annapurna Labs, the chip-design unit inside AWS. Annapurna has not said which of its products will use NVHBM, and Nvidia has not named any other customer.
Marvell announced a base-die-controller memory design in December 2024, with Micron, Samsung, and SK hynix publicly attached as collaborators and a claim of up to 25% more compute area. Marvell sells custom silicon to hyperscalers without the interconnect gate, which is the contrast Nvidia does not address. The two efforts differ in business model as much as in silicon: Marvell's coalition runs through the standard JEDEC ecosystem and a wider supplier base, while Nvidia's runs through NVLink Fusion and the customers Nvidia chooses to admit.
The gating matters more than the percentages right now, because the percentages are uncheckable for at least another year. The watch item is HBM4E volume shipments: once real parts ship, the 30/15/25 numbers can be reproduced or refuted. The wider question is whether base-die controllers become a JEDEC-standard option any accelerator maker can license, which is the path Marvell's coalition is already walking, or stay bound to NVLink Fusion and the customers Nvidia chooses to admit. Either outcome reshapes who can build a competitive AI accelerator in 2027 and after.