QCNEWS
French photonic quantum chipmaker Quandela and NVIDIA publish a joint wiring diagram that puts light based quantum processors next to GPU racks, with a sub 4µs interconnect as the engineering bet.
NVIDIA and Quandela's joint paper treats hybrid quantum-classical compute as a rack-level engineering problem. A photonic quantum processor becomes useful, the white paper argues, the moment it can sit in the same physical aisle as a row of Hopper or Blackwell GPUs, answer in single-digit microseconds, and run inside a CUDA-Q process the operators already know. The qubit count stops being the story; the latency budget does.
The paper was presented at IEEE Quantum Week 2026 in Toronto and is, in practice, a wiring diagram for hybrid compute. Quandela is the French photonic quantum chipmaker behind the MosaiQ processor; NVIDIA supplies the GPU side and the NVQLink interconnect, a low-latency path between quantum control electronics and the GPU host. The two companies argue that, with the right glue, a light-based quantum chip can live next to a GPU rack instead of behind a remote cloud API. That is a different pitch from a qubit-count headline, and it tells the reader where the engineering bet has moved.
The load-bearing claim is the interconnect. NVQLink is built on Remote Direct Memory Access over Converged Ethernet (RoCE), a network protocol that moves data between machines with very small delay. The white paper budgets a sub-4-microsecond round-trip between a GPU node and the Quandela Quantum System Controller (QSC), the FPGA-based box that generates the laser pulses and reads photon detections from MosaiQ. Four microseconds is not a quantum speedup. It is the engineering ceiling that lets a hybrid application keep a tight feedback loop: the GPU prepares a state, the QPU runs a short circuit, the GPU decodes an error-correction round, and the loop repeats, all inside a single process. Below that budget, the classical and quantum halves stop thrashing each other and start to look like one computer.
That latency is what makes the rest of the stack possible. The software side pairs NVIDIA's CUDA-Q and cuQuantum libraries with MerLin, Quandela's open-source quantum machine learning framework, plus photonic digital twins of the hardware. On a Hopper or Blackwell node, that combination can run state-vector and tensor-network simulations, real-time quantum error correction decoding, and automated QPU pulse calibration in the same host process. The point is not to show quantum advantage on any one workload. The point is to remove the wall between the GPU cluster and the QPU so that someone, somewhere, can find a workload where the hybrid loop beats either side alone.
The commercial roadmap is structured in three phases, and reading them in order tells the reader how seriously to take each claim.
Phase one is Access: cloud-hosted experimentation, where customers run jobs against a Quandela QPU exposed through NVQLink, with NVIDIA's CUDA-Q stack on the host side. This is shipping today as a sandbox for hybrid application discovery.
Phase two is Integration and Discovery. This is where the architecture in the white paper actually lives. Customers put a photonic QPU on-premises next to their own GPU cluster, profile real workloads against the sub-4µs budget, and figure out which hybrid kernels are worth the cost of co-location. The leads named on the work are Quandela's chief technology and product officer Jean Senellart and NVIDIA's director of quantum product Sam Stanwyck.
Phase three is Scale, and it is the phase the reader should hold at arm's length. Scale depends on SPOQC, Quandela's spin-optical quantum computing architecture, a different hardware path from the MosaiQ chip used in the first two phases. The white paper treats SPOQC as the route to fault tolerance, but the architecture has not been demonstrated at scale in any public benchmark. The diagram in the paper is years ahead of any deployed fault-tolerant machine, and the three-phase structure is best read as a research path with a commercial label, not a product roadmap.
There is a useful constraint to keep on the piece. This is a vendor joint white paper, not a peer-reviewed result, and there is no independent third-party validation of the sub-4-microsecond latency figure or the workloads the architecture is supposed to enable. The architecture is a proposal from the companies best positioned to benefit if the proposal is adopted. The Access phase is real, the Integration phase is a published design, and the Scale phase is a research bet dressed in a product label. The honest read is that the integration question, how a photonic QPU physically lives next to a GPU rack, under what latency, on what software stack, has now been put on the table in public, and the rest of the answer is still the work.