HWNEWS
Brain inspired chips promise low power AI, but the field has stalled on software, benchmarks, and shared access. A Nature review and a new national labs program try to fix that.
Katie Schuman sits down at Oak Ridge's Summit or Frontier, among the world's largest supercomputers, and uses it to simulate a brain-shaped chip that, if it existed, would draw a fraction of the power of a conventional GPU. The asymmetry is the point, and the field's tell.
For two decades, "neuromorphic" computing, hardware that mimics the brain's parallel, event-driven, low-power style, has promised to break AI's appetite for electricity. A handful of commercial chips exist, including Intel's Hala Point and IBM's TrueNorth, plus a long shelf of research prototypes. Almost none of them have escaped the lab. A Nature review co-authored by Schuman, and 22 other researchers names the real reason: not the silicon, but everything around it.
The review, "Neuromorphic Computing at Scale," argues the field has over-rotated on novel chips while under-investing in the software, toolchains, shared benchmarks, and access infrastructure that turn a clever prototype into a usable computing paradigm. Schuman is also a co-investigator on THOR, the Neuromorphic Commons, a DOE-backed effort to broaden access to neuromorphic systems the way national labs already make supercomputers available to academic researchers. The argument is laid out in the EE Times feature "Neuromorphic Computing Needs More Than Novel Chips."
The diagnosis is structural. Neuromorphic systems differ from conventional chips in four ways: processing and memory live next to each other instead of being separated by a slow bus; computation is massively parallel rather than clock-synchronous; signals are sparse and event-driven, firing only when something changes; and the whole stack is designed for low power, often orders of magnitude below a GPU at the same task. None of those properties are new. The bottleneck is the layer above the chip.
That layer is what most readers will recognize as a "paradigm" in the Kuhnian sense: the working assumptions, tools, and shared benchmarks that let a research community turn prototype results into something an engineer can build on. Conventional computing has it: CUDA, PyTorch, MLPerf, a public cloud. Neuromorphic computing has a research culture, a few open frameworks (Intel's Lava is the most cited, per the Patsnap 2025 ecosystem report), and a small handful of community benchmarks. The Nature review's central claim is that without the surrounding stack, compilers, training algorithms that work on spiking data, reproducible benchmarks, shared hardware access, the chip side alone cannot carry the field.
The honest counterargument is that the toolchain side has tried before. Intel's Lava, IBM's TrueNorth ecosystem, and earlier SpiNNaker-era software stacks have not produced breakout adoption. Schuman and her co-authors acknowledge as much: novel software and a shared access layer are necessary, but they are not sufficient if the underlying hardware does not give application developers a clear reason to switch. The chip side is part of the bottleneck, not separate from it.
THOR / Neuromorphic Commons is the institutional response. By making neuromorphic systems available through the same access channels researchers use to get time on Summit, Frontier, and other leadership-class machines, the program tries to lower the experimentation cost for outside groups. If a graduate student at a university without its own neuromorphic testbed can run a real workload on THOR, the field gets a larger population of people who know what the chips can and cannot do.
That is the engineering question the Nature review is really asking: can the community build the surrounding stack fast enough that the next round of chips, and the academic work that depends on them, is judged on what the systems actually do, not on what brain-shaped computing might one day be good for? Schuman's day job, using the world's largest supercomputers to simulate a low-power chip that does not yet exist in hardware, is a working answer: simulate until the silicon catches up, and build the layer around it in parallel. The first THOR cohort's benchmark numbers will be the public test of whether the layer is being built fast enough.