GlobalFoundries is stitching together CPU, AI accelerator, network on chip, safety toolchain, and reference silicon as one package — and betting that for Physical AI at the edge, the unit of sale is a kit, not a core.
GlobalFoundries paid for MIPS to bundle, not just to license. Chief executive Sameer Wasson and chief technology officer Yankin Tanurhan call the bet "software-to-silicon" in an EE Times interview: stop selling processor cores in isolation and start shipping CPU, neural-network accelerator, network-on-chip, safety tooling, and reference silicon as one package. Physical AI at the edge (agentic models running on cars, robots, and factory equipment) is the proof-of-concept.
In January, MIPS launched the S8200, a software-first RISC-V neural processing unit aimed at transformer and agentic language models at the edge, with multimodal inputs (vision, radar, speech) and silicon reference platforms expected to sample in 2027, per the company's announcement and a BusinessWire distribution. The NPU targets PyTorch, ONNX, and emerging agentic runtimes without forcing customers to rewrite for a custom ISA. HyperFRAME Research's analysis calls the same market the one that "makes MIPS impossible to ignore".
The S8200 has at least one program-of-record validation: ForwardEdge ASIC, a Lockheed Martin wholly owned subsidiary, selected the core for an upcoming high-performance ASIC targeting autonomous platforms. The defense/aerospace posture is a qualification signal, not a commercial design win, and the segment is the kind of customer a new ISA vendor needs to land first.
Two Embedded World announcements fill out the stack. MIPS and INOVA Semiconductors unveiled a robotics-control reference platform for advanced humanoids, pairing MIPS' M8500 application core and S8200 NPU with INOVA's APXpress chip-to-chip interface on GlobalFoundries' FDX process, per a MIPS press release. The same day, MIPS and Green Hills Software announced a jointly developed Safety SDK for the M8500 targeting ASIL-D and SIL 3/4 certification workflows (motor control, traction inverters, battery management, industrial robotics), integrating Green Hills' MULTI toolchain, optimizing C/C++ compilers, and µ-velOSity RTOS, per a separate release. The SDK is a tooling and workflow claim, not a certified product.
MIPS disclosed a partnership with Arteris (Nasdaq: AIP) on April 21, 2026 to adopt FlexGen smart NoC IP plus Magillem connectivity and register-automation tools, extending a 2024 RISC-V SoC collaboration, per the companies' announcement. A NoC is the on-die fabric that ties compute, memory, and accelerators together; choosing it, with the automation software that connects it to register and IP blocks, is what lets a vendor ship a stack rather than a parts catalog.
GlobalFoundries has agreed to acquire Synopsys' ARC processor IP line, which includes ARC-V (RISC-V), ARC-Classic, ARC VPX-DSP, ARC NPX NPU, and ASIP tools; the deal is expected to close in the second half of 2026, subject to closing conditions, per a MIPS release. On close, MIPS and ARC together would be pitched as the largest RISC-V IP provider by headcount. Synopsys' strategic narrowing toward interface and foundation IP, covered by Financial Content, is the tell: a major incumbent decided processor IP was not where it wanted to compete.
MIPS' offer, post-ARC close, is to sell five pieces in one order: a CPU, an NPU that runs modern model formats, a NoC that ties them together, a safety toolchain for certification, and a reference design that already works in the foundry's process. Green Hills supplies the safety piece, Arteris supplies the NoC, INOVA supplies a robotics reference, the S8200 supplies the AI accelerator, and GlobalFoundries' process and packaging supply the silicon. The Green Hills SDK targets the same ASIL-D and SIL 3/4 workflows that Arm's Cortex-R and Cortex-M safety cores own in automotive MCUs, putting a RISC-V competitor with a pre-wired certification path into Arm's most entrenched turf. The bet isn't that RISC-V will replace Arm on laptops. It is that the unit of sale for embedded processor IP is shifting from cores to kits.
Three dates will show whether the bundle reaches production on the schedule buyers need: the H2 2026 ARC close, the 2027 sampling of S8200 silicon reference platforms, and the first ASIL-D certification of an M8500 design under the Green Hills SDK.