HWBRIEF
Marvell's Bravera SC6 SSD controller, Structera CXL (Compute Express Link) memory expansion chips, and Photonic Fabric components each target a different layer of the AI rack, framed as a 'memory disaggregation' play.
Marvell Technology is grouping three of its memory and storage products under a single "memory disaggregation" strategy aimed at easing data-flow bottlenecks in AI infrastructure, according to a briefing with EE Times.
The chipmaker's associate VP of product marketing, Khurram Malik, walked the publication through the portfolio. At the server level, the Bravera SC6 is a PCIe 6.0 SSD controller for AI storage use cases such as key-value caching, where keeping more data on flash improves efficiency. It supports cross-NAND-vendor interoperability and uses a host-managed flash translation layer for write-amplification and wear-leveling control.
At the rack level, the Structera CXL family handles memory expansion and pooling. Compute Express Link is a memory-interconnect standard that lets a server tap DRAM or persistent memory on a sibling device; the spec predates the current AI boom but has become a key enabler for rack-scale memory sharing, Marvell said. Structera X, positioned as a likely first adoption point, reuses existing DDR4 or DDR5 capacity.
Above the rack, Photonic Fabric components target shared memory across multiple racks using fiber-optic links.
Marvell's framing: each layer addresses where data sits relative to the compute doing inference, not how fast the memory itself runs. The pitch to hyperscalers and cloud providers is improved token efficiency on inference workloads. What remains unverified is whether large cloud operators buy a stack-spanning memory strategy from one vendor or keep building vertically in-house.